Patents by Inventor Aleksey Gorelov

Aleksey Gorelov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Systems and methods for managing inter-CPU interrupts between multiple CPUs
    Patent number: 9965414
    Abstract: Methods for managing inter-CPU interrupts between sending and receiving CPUs are disclosed. As a part of a method, a target CPU identifier and an interrupt number is written in an interrupt send register of an interrupt sending CPU, the interrupt number is written into one of a plurality of locations of an interrupt receive register corresponding to the target CPU, an identifier of the location of the highest priority interrupt of a plurality of interrupts received by the interrupt receive register is written in an interrupt pick register, the interrupt pick register is read to determine the highest priority interrupt and a matrix associated with the target CPU is read to determine the sender of the highest priority interrupt. The highest priority interrupt is processed.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: May 8, 2018
    Assignee: INTEL CORPORATION
    Inventors: Karthikeyan Avudaiyappan, Aleksey Gorelov
  • SYSTEMS AND METHODS FOR MANAGING INTER-CPU INTERRUPTS BETWEEN MULTIPLE CPUs
    Publication number: 20170255576
    Abstract: Methods for managing inter-CPU interrupts between sending and receiving CPUs are disclosed. As a part of a method, a target CPU identifier and an interrupt number is written in an interrupt send register of an interrupt sending CPU, the interrupt number is written into one of a plurality of locations of an interrupt receive register corresponding to the target CPU, an identifier of the location of the highest priority interrupt of a plurality of interrupts received by the interrupt receive register is written in an interrupt pick register, the interrupt pick register is read to determine the highest priority interrupt and a matrix associated with the target CPU is read to determine the sender of the highest priority interrupt. The highest priority interrupt is processed.
    Type: Application
    Filed: May 23, 2017
    Publication date: September 7, 2017
    Inventors: Karthikeyan Avudaiyappan, Aleksey Gorelov
  • Systems and methods for managing inter-CPU interrupts between multiple CPUs
    Patent number: 9678903
    Abstract: Methods for managing inter-CPU interrupts between sending and receiving CPUs are disclosed. As a part of a method, a target CPU identifier and an interrupt number is written in an interrupt send register of an interrupt sending CPU, the interrupt number is written into one of a plurality of locations of an interrupt receive register corresponding to the target CPU, an identifier of the location of the highest priority interrupt of a plurality of interrupts received by the interrupt receive register is written in an interrupt pick register, the interrupt pick register is read to determine the highest priority interrupt and a matrix associated with the target CPU is read to determine the sender of the highest priority interrupt. The highest priority interrupt is processed.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: June 13, 2017
    Assignee: Intel Corporation
    Inventors: Karthikeyan Avudaiyappan, Aleksey Gorelov