Abstract: A host system performs I/O processing functions traditionally performed on storage systems. Metadata about data stored on the storage system may be stored on the host system, including metadata about the data stored in a cache of the storage system. The SSI may be configured to determine whether an I/O operation is a read or write operation. If the I/O operation is a read operation, the SSI may determine from metadata stored thereon whether the data to be read is in cache. If the data is in cache, the SSI may read the data directly from cache over the internal fabric without use of CPU resources of a director, and, in some embodiments, without use of a director at all. If the data is not in cache, the SSI may read the data directly from the physical storage device over the internal fabric without use of a director.

Abstract: A method, computer program product, and computer system for identifying, by a computing device, a trigger event associated with an Ethernet switch. Ethernet based control information may be encapsulated into an InfiniBand based packet. The InfiniBand based packet with the Ethernet based control information may be transmitted over the InfiniBand fabric from a source to a destination. The Ethernet based control information may be decapsulated from the InfiniBand based packet at the destination.

Abstract: Compressing data of a storage device includes selecting a portion of data for data compression that is predicted to be unlikely to be accessed, selecting a particular one of a plurality of data compression algorithms to apply to the portion according to a frequency value associated with each of the data compression algorithms, and adjusting the frequency value of the particular one of a plurality of data compression algorithms according to performance of the particular one of a plurality of data compression algorithms. The performance may vary according to a ratio of amount of compression achieved to processing cycles of a processor used to compress the portion of data. The processor may perform storage device functions that are separate from data compression. The portion of data may be selected from a plurality of logical devices used in connection with a single application that accesses the storage device.

Abstract: A parallel decompression engine has separate hardware paths for sequence processing and repeated byte copying/placement. Literal byte extraction logic obtains literal bytes from a selected sequence. Literal byte write logic writes the obtained literal bytes into an uncompressed data set that is being generated. Offset and length extraction logic obtains the offset and length of repeated bytes from the selected sequence. In a separate hardware path, copying and placement logic uses the offset and length to find and copy the length of repeated bytes at the specified offset in the uncompressed data set, and place the copied repeated bytes back into the uncompressed data set adjacent to the literal bytes.

Abstract: Storage node blades in a data storage system utilize queue pairs associated with point-to-point links to perform RDMA transactions with memory components associated with other storage node blades. Higher quality of service queue pairs are used for system message transactions and lower quality of service queue pairs are used for remote direct memory access data. Postings to a relatively higher priority queue pair are reduced when a corresponding relatively lower priority queue pair between the same pair of storage nodes via the same switch is starved of bandwidth. Postings to the relatively higher priority queue pair are increased when bandwidth starvation is remediated.

Abstract: A data storage system has first and second computing nodes that are interconnected by a switchless fabric. Each storage node includes first and second paired storage directors with an interconnecting communication link. Atomic operations sent between the computing nodes are mediated by network adapters. Atomic operations sent between paired storage directors via the interconnecting communication link are provided to a network adapter via an internal port and mediated by network adapter. The interconnecting communication links can be used as a backup path for atomic operations in the event of a link failure of the switchless fabric.

Abstract: Individual transport connections within a dual-star fabric connected multi-node storage system are disabled in response to associated failures due to faulty hardware or temporal congestion. Each configured IB transport connection is monitored for viability and, upon failure, removed from the pool of available resource. Following failure restoration the resource is tested to ensure proper functionality and then restored to the pool of resources. Mappings associated with the transport connections are maintained while the connections are disabled.

Abstract: Described are techniques for processing a request to access global memory. For a first processor included on a first of a plurality of boards connected by a fabric, a logical address is determined for a global memory location in a system global memory. A first physical address for the logical address is determined. It is determined whether the first physical address is included in a first global partition of the first board. If so, first processing is performed including updating a memory map to map a window of the first processor's logical address space to a physical memory segment located within the first global partition. Otherwise, if the first physical address is included in a second of the plurality of global partitions physically located on one of the plurality of boards other than said first board, second processing is performed to issue the request over the fabric.

Abstract: Described are techniques for partitioning memory. A plurality of boards is provided. Each of the plurality of boards includes a physical memory portion and a set of one or more processor. The physical memory portion in each of said plurality of boards is partitioned into a plurality of logical partitions including a global memory partition accessible by any processor on any of the plurality of boards and one or more other memory partitions configured for use by one or more processors of said each board. Each of the one or more other memory partitions not being accessible to a processor on a board other than said each board.

Abstract: Detecting data errors in connection with a data transfer process includes performing an XOR operation on a plurality of data blocks to obtain a data block XOR result. An XOR operation may be performed on a plurality of cyclic redundancy check (CRC) codes associated with the plurality of data blocks to obtain a CRC XOR result. The data block XOR result and the CRC XOR result may be used to determine whether an error exists in the plurality of data blocks. The system may be used in connection with local IO transfers and in connection with local CPU XOR operations for a RAID system in which data may be mirrored, striped or otherwise distributed across multiple storage devices.

Abstract: An apparatus and method are provided for connecting a host Enterprise System Connection Architecture (ESCON) Input/Output (I/O) interface to a cache of a data storage system. The apparatus includes (a) a set of at least 4 pipelines, each pipeline being coupled on a first end to the host ESCON I/O interface and being coupled on a second end to the cache, (b) a plurality of line processors, each line processor controlling one or more of the pipelines of the set of pipelines, and (c) in each pipeline, a protocol engine, the protocol engine configured to distinguish user data from frame header data and separate the user data from the frame header data for transport over the pipeline.

Abstract: An apparatus and method are provided for connecting a host Enterprise System Connection Architecture (ESCON) Input/Output (I/O) interface to a cache of a data storage system. The apparatus includes (a) a set of at least 4 pipelines, each pipeline being coupled on a first end to the host ESCON I/O interface and being coupled on a second end to the cache, (b) a plurality of line processors, each line processor controlling one or more of the pipelines of the set of pipelines, and (c) in each pipeline, a protocol engine, the protocol engine configured to distinguish user data from frame header data and separate the user data from the frame header data for transport over the pipeline.

Abstract: A shared resources service processor facilitates messaging between line processors and provides a single point of contact for a user interfacing with line processor(s), for example in a storage system interface. Shared memory is divided into “mailboxes” that are used to communicate between the line processors and the service processor. The service processor issues a system management interrupt to any or all of the line processors. This interrupt indicates to the line processor(s) that it should go out to the shared memory and read its respective mailbox. In operation, the service processor can deliver a message, i.e. command, to a line processor's mailbox, for example to tell a line processor to go off-line or on-line. The service processor will write the command into the mailbox and then assert the system management interrupt on the appropriate line processor that it wants to read the mailbox.

Abstract: A shared resources service processor facilitates messaging between line processors and provides a single point of contact for a user interfacing with line processor(s), for example in a storage system interface. Shared memory is divided into “mailboxes” that are used to communicate between the line processors and the service processor. The service processor issues a system management interrupt to any or all of the line processors. This interrupt indicates to the line processor(s) that it should go out to the shared memory and read its respective mailbox. In operation, the service processor can deliver a message, i.e. command, to a line processor's mailbox, for example to tell a line processor to go off-line or on-line. The service processor will write the command into the mailbox and then assert the system management interrupt on the appropriate line processor that it wants to read the mailbox.