Abstract: A digital-to-analog converter (DAC). A DAC includes a plurality of DAC cells and a controller. The controller generates a control signal for driving the plurality of DAC cells for each clock cycle. The controller may generate the control signal to select a set of one or more DAC cells for an input code or for a standby mode of the DAC such that the selected set of one or more DAC cells to be active for the same input code or for the standby mode of the DAC change over time without affecting an output of the DAC more than a predetermined limit.

Abstract: An inverter circuit is provided. The inverter circuit includes a first node for coupling to a first electrical potential and a second node for coupling to a second electrical potential different from the first electrical potential. Further, the inverter circuit includes a third node configured to output an output signal of the inverter circuit. The inverter circuit includes a plurality of transistors of a first conductivity type coupled in series between the first node and the third node. Additionally, the inverter circuit includes a plurality of transistors of a second conductivity type coupled in series between the third node and the second node. The second conductivity type is different from the first conductivity type. The inverter circuit further includes at least one coupling path comprising a capacitive element.