Patents by Inventor Alessandra Nardi
Alessandra Nardi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11416662Abstract: Embodiments disclosed herein describe systems, methods, and products for safety verification of an IC design. A computer executing an illustrative EDA tool may perform a static cone of influence (COI) analysis of a gate-level netlist of the IC design to determine whether faults injected at combinational logic at different COIs are safe or dangerous. The computer may leverage this determination to perform a register-transfer level (RTL) simulation by generating and injecting equivalent faults to sequential logic in the IC design. The computer may further flexibly allow RTL simulations under different assumptions based upon downstream observability of the faults injected to the sequential logic. Because, RTL simulations are significantly faster than the gate-level simulations, the computer may efficiently calculate DC of one or more safety mechanism in the IC design.Type: GrantFiled: January 8, 2020Date of Patent: August 16, 2022Assignee: CADENCE DESIGN SYSTEMS, INC.Inventors: Antonino Armato, Francesco Lertora, Alessandra Nardi
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Patent number: 10853545Abstract: Devices, methods, non-transitory computer readable media, and other embodiments are described for automatic gate-level functional safety (FS) analysis and associated circuit design operations. One embodiment involves accessing register transfer level (RTL) design data, and accessing a set of FS data associated with an initial circuit design describing one or more failure modes associated with a plurality of circuit elements, an associated FS design criterion for each failure mode of the one or more failure modes, and one or more associations between the plurality of circuit elements and the one or more failure modes. The embodiment then involves generating a gate-level netlist using the RTL design data, mapping the one or more associations between the plurality of circuit elements from the RTL design data and the one or more failure modes to the gate-level netlist, and generating an updated set of FS data using the mapping of the one or more associations to the gate-level netlist.Type: GrantFiled: August 30, 2019Date of Patent: December 1, 2020Assignee: Cadence Design Systems, Inc.Inventors: Alessandra Nardi, Francesco Lertora, Antonino Armato, Deepak Soi
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Patent number: 10643011Abstract: Devices, methods, computer readable media, and other embodiments are described for design and verification of safety critical electronic systems. Some embodiments integrate functional safety (FS) data with circuit design data for use in electronic design automation (EDA) operations. One embodiment involves a device accessing FS and circuit design data; automatically analyzing register transfer level (RTL) design data using the FS data to perform one or more FS quality checks; and placing and routing the circuit design using the RTL design data and the set of FS data to perform FS-aware placement and routing. In some embodiments, failure modes and associated safety mechanisms to improve safety metrics associated with failure modes are automatically added to the circuit design during EDA operations. In other embodiments, additional FS-aware operations are performed. In some embodiments, the FS data is structured as a single Unified Safety Format (USF) file.Type: GrantFiled: June 29, 2018Date of Patent: May 5, 2020Assignee: Cadence Design Systems, Inc.Inventors: Alessandra Nardi, Antonino Armato
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Patent number: 9576098Abstract: A method for performing leakage analysis includes receiving information specifying an integrated circuit. A neighborhood of shapes associated with the integrated circuit is then determined. Leakage information associated with the integrated circuit is generated based on the neighborhood of shapes. The neighborhood of shapes may be determined by determining a first set of spacings to a boundary of a first cell from an internal shape. A second set of spacings may be determined from the boundary of the first cell to a shape of a second cell. A lithography process may be characterized using the first and second set of spacings.Type: GrantFiled: October 29, 2013Date of Patent: February 21, 2017Assignee: Synopsys, Inc.Inventors: Emre Tuncer, Hui Zheng, Vivek Raghavan, Anirudh Devgan, Amir Ajami, Alessandra Nardi, Tao Lin, Pramod Thazhathethil, Alfred Wong
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Publication number: 20140181762Abstract: A method for performing leakage analysis includes receiving information specifying an integrated circuit. A neighborhood of shapes associated with the integrated circuit is then determined Leakage information associated with the integrated circuit is generated based on the neighborhood of shapes. The neighborhood of shapes may be determined by determining a first set of spacings to a boundary of a first cell from an internal shape. A second set of spacings may be determined from the boundary of the first cell to a shape of a second cell. A lithography process may be characterized using the first and second set of spacings.Type: ApplicationFiled: October 29, 2013Publication date: June 26, 2014Inventors: Emre Tuncer, Hui Zheng, Vivek Raghavan, Anirudh Devgan, Amir Ajami, Alessandra Nardi, Tao Lin, Pramod Thazhathethil, Alfred Wong
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Patent number: 8572523Abstract: A method for performing leakage analysis includes receiving information specifying an integrated circuit. A neighborhood of shapes associated with the integrated circuit is then determined. Leakage information associated with the integrated circuit is generated based on the neighborhood of shapes. The neighborhood of shapes may be determined by determining a first set of spacings to a boundary of a first cell from an internal shape. A second set of spacings may be determined from the boundary of the first cell to a shape of a second cell. A lithography process may be characterized using the first and second set of spacings.Type: GrantFiled: July 20, 2007Date of Patent: October 29, 2013Assignee: Synopsys, Inc.Inventors: Emre Tuncer, Hui Zheng, Vivek Raghavan, Anirudh Devgan, Amir Ajami, Alessandra Nardi, Tao Lin, Pramod Thazhathethil, Alfred Wong
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Patent number: 8473876Abstract: A method for performing timing analysis includes receiving information specifying an integrated circuit. A neighborhood of shapes associated with the integrated circuit is then determined. Delay information associated with the integrated circuit is generated based on the neighborhood of shapes. The neighborhood of shapes may be determined by determining a first set of spacings to a boundary of a first cell from an internal shape. A second set of spacings may be determined from the boundary of the first cell to a shape of a second cell. A lithography process may be characterized using the first and second set of spacings.Type: GrantFiled: July 20, 2007Date of Patent: June 25, 2013Assignee: Synopsys, Inc.Inventors: Emre Tuncer, Hui Zheng, Vivek Raghavan, Anirudh Devgan, Amir Ajami, Alessandra Nardi, Tao Lin, Pramod Thazhathethil, Alfred Wong
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Patent number: 8307317Abstract: A statistical on-chip variation approach to timing analysis permits the automated or semi-automated selection of design-specific margins without requiring complex statistical libraries. By separately addressing the impact of random and systematic variations on timing, a design-specific margin can be obtained and used in downstream OCV analysis. In addition, where statistical libraries are available for some portions of a design, these can be incrementally included in the timing analysis to obtain more accurate results.Type: GrantFiled: August 1, 2011Date of Patent: November 6, 2012Assignee: Synopsys, Inc.Inventors: Amzie Adams, Alessandra Nardi
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Publication number: 20110289465Abstract: A statistical on-chip variation approach to timing analysis permits the automated or semi-automated selection of design-specific margins without requiring complex statistical libraries. By separately addressing the impact of random and systematic variations on timing, a design-specific margin can be obtained and used in downstream OCV analysis. In addition, where statistical libraries are available for some portions of a design, these can be incrementally included in the timing analysis to obtain more accurate results.Type: ApplicationFiled: August 1, 2011Publication date: November 24, 2011Inventors: Amzie Adams, Alessandra Nardi
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Patent number: 7992114Abstract: A statistical on-chip variation approach to timing analysis permits the automated or semi-automated selection of design-specific margins without requiring complex statistical libraries. By separately addressing the impact of random and systematic variations on timing, a design-specific margin can be obtained and used in downstream OCV analysis. In addition, where statistical libraries are available for some portions of a design, these can be incrementally included in the timing analysis to obtain more accurate results.Type: GrantFiled: August 19, 2008Date of Patent: August 2, 2011Assignee: Magma Design Automation, Inc.Inventors: Amzie Adams, Alessandra Nardi
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Patent number: 7458049Abstract: A system and a method are disclosed for circuit analysis. A circuit modeling system calculates sensitivities of gates for statistical static timing analysis of a circuit. Timing distribution sensitivities of gates and correlations between the sensitivities are determined. A Monte Carlo simulation is run using the sensitivities to determine timing distribution of paths and determine probabilities of paths being the critical path. Aggregate sensitivities for cells are also determined.Type: GrantFiled: June 12, 2006Date of Patent: November 25, 2008Assignee: Magma Design Automation, Inc.Inventors: Emre Tuncer, Alessandra Nardi, Srinath R. Naidu, Aliaksandr Antonau
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Publication number: 20080052646Abstract: A method for performing leakage analysis includes receiving information specifying an integrated circuit. A neighborhood of shapes associated with the integrated circuit is then determined. Leakage information associated with the integrated circuit is generated based on the neighborhood of shapes. The neighborhood of shapes may be determined by determining a first set of spacings to a boundary of a first cell from an internal shape. A second set of spacings may be determined from the boundary of the first cell to a shape of a second cell. A lithography process may be characterized using the first and second set of spacings.Type: ApplicationFiled: July 20, 2007Publication date: February 28, 2008Applicant: Magma Design Automation, Inc.Inventors: Emre Tuncer, Hui Zheng, Vivek Raghavan, Anirudh Devgan, Amir Ajami, Alessandra Nardi, Tao Lin, Pramod Thazhathethil, Alfred Wong
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Publication number: 20080052653Abstract: A method for performing timing analysis includes receiving information specifying an integrated circuit. A neighborhood of shapes associated with the integrated circuit is then determined. Delay information associated with the integrated circuit is generated based on the neighborhood of shapes. The neighborhood of shapes may be determined by determining a first set of spacings to a boundary of a first cell from an internal shape. A second set of spacings may be determined from the boundary of the first cell to a shape of a second cell. A lithography process may be characterized using the first and second set of spacings.Type: ApplicationFiled: July 20, 2007Publication date: February 28, 2008Applicant: Magma Design Automation, Inc.Inventors: Emre Tuncer, Hui Zheng, Vivek Raghavan, Anirudh Devgan, Amir Ajami, Alessandra Nardi, Tao Lin, Pramod Thazhathethil, Alfred Wong