Abstract: A power MOSFET driver circuit includes a feedback circuit configured to supply a feedback signal that signals when a gate voltage of the power MOSFET crosses a plateau value and the power MOSFET switches conduction state. The feedback circuit includes a comparator with a replica MOSFET of the power MOSFET, with scaled down dimensions, whose gate is coupled to the gate electrode of the power MOSFET. A bistable circuit has an input coupled to an output of the replica MOSFET and is configured to change a logic state of the feedback signal following the transition of the switching signal when the gate voltage of the power MOSFET crosses the plateau value and the power MOSFET switches conduction state.

Abstract: Drive signals for switching stages of a multiphase electronic converter are generated as a function of a PWM signal and a current balancing circuit. The current balancing circuit receives a control clock signal and a reference clock signal from a phase shift circuit. A phase detector generates the PWM signal as a function of the control clock signal received via one or more delay lines and the reference clock signal. Specifically, a regulator circuit of the current balancing circuit varies the delay introduced by the one or more delay lines in order to balance the currents provided by the switching stages of the multiphase electronic converter.

Abstract: A DC-DC converter circuit receives a supply voltage and an adjustable first reference voltage to generate a DC supply voltage as a function of the adjustable first reference voltage. A LDO regulator circuit receives the DC supply voltage to generate a regulated output voltage. A power transistor of the LDO regulator circuit has drain where the regulated output voltage is generated and a gate controlled by a gate voltage. A headroom control circuit generates the adjustable first reference voltage using a scaled replica of the power transistor in a trans-diode configuration having a source coupled to a drain of the power transistor. A resistor is connected to a drain of the scaled replica transistor and biased to generate a gate reference voltage. A reference voltage generator circuit generates the adjustable first reference voltage as a function of a difference between the gate voltage and the gate reference voltage.

Abstract: Disclosed herein is a DC-DC converter with an improved time-domain control system. The converter includes a DC-DC converter circuit, a feedback network, a high-pass filter, and a time-domain proportional-integral compensator circuit. The compensator circuit receives a feedback voltage and a filtered voltage, generates oscillating signals based on these voltages, and produces a drive signal by comparing the oscillating signals. Driver circuits control the converter circuit based on this drive signal. The time-domain compensator circuit includes transconductors, current-controlled oscillators, and a phase detector, implementing proportional-integral control in the time domain without delay lines. This approach offers improved response time and efficiency compared to traditional voltage-based or digital control methods.

Abstract: Circuitry for detecting a short across an inductor of a DC-DC converter includes a decoupling-circuit coupled between an inductor-terminal and an intermediate-node that, when activated, generates a detection-voltage (representative of voltage at the inductor-terminal) at the intermediate-node. A logic-circuit has an input coupled to the intermediate-node and an output generating a detection-signal. The detection-signal is asserted when the detection-voltage is closer to an input-voltage to the DC-DC converter than ground but is deasserted when the detection-voltage is closer to ground. Control-circuitry, at the beginning of a high-side conduction-phase, activates the decoupling-circuit and delays for a delay-period. After expiration of the delay-period and in response to the detection-signal being asserted, the control-circuitry completes the high-side conduction-phase.

Abstract: This disclosure describes a DC-DC converter with improved response to input voltage variations. The converter employs a feedback-PID structure with a fast injection circuit and fine correction circuit to regulate output voltage. The fast injection circuit produces rapid duty cycle adjustments in response to input voltage changes, implementing a feedforward path. The fine correction circuit works with the fast injection circuit to provide integral action. A low-pass filter and the fine correction circuit create a bandpass filtering. The control loop includes a proportional-integral and a phase detection circuit to generate the final driving signal. A multiplier circuit tracks the input voltage and produces a control current proportional to the steady-state duty cycle. This approach enables fast response to input variations and precise long-term regulation while effectively managing noise across different frequency ranges.

Abstract: A hybrid DC-DC converter includes a first capacitor coupled between first and second nodes, a second capacitor coupled between third and fourth nodes, and a third capacitor coupled between fifth and sixth nodes. An inductor is coupled between the second node and an output. Each switching cycle of the converter includes a first phase where the first node is coupled to an input, the second and third nodes are coupled to each other, the fourth node is coupled to ground, the fifth node is coupled to the output, and the sixth node is coupled to ground. The switching cycle further includes a last phase where the first, fourth and fifth nodes are coupled to each other, the second node is coupled to ground, the third node is coupled to the input, and the sixth node is coupled to the output.

Abstract: A boost DC-DC converter includes a switching network, coupled to an inductor, controlled by a PWM driving signal. A control loop receives a voltage output and provides the PWM driving signal. The control loop generates an error signal as a function of a difference between voltage output voltage and a reference, with the PWM driving signal generated based on the error signal. A low pass filter circuit within the control loop receives the PWM driving signal and provides at least one filtered signal. An adder node of the control loop receives the at least one filtered signal from the low pass filter circuit for addition to the at least one filtered signal. The PWM driving signal is generated as a function of a sum of the filtered signal and the error signal.

Abstract: A correction circuit for a switching converter counters undesired reduction of switching frequency in response to a decrease in a load current at a converter output node. Detection circuitry receives a reference clock signal indicative of a lower bound for the switching frequency of the converter and a pulsed drive signal indicative of the switching frequency of the converter. In response to the switching frequency of the converter falling below said lower bound for the switching frequency of the converter, the detection circuitry produces an error signal. Current sink circuitry coupled to the output node of the converter sinks from the output node of the converter corrective current in response to receipt of the error signal from the detection circuitry.

Abstract: In a multi-level hybrid DC-DC converter with a flying capacitor, a feedback circuit includes a first oscillator and produces a first clock signal with a frequency dependent on an output voltage. A second oscillator produces a second clock signal having a frequency dependent on a reference voltage. A logic circuit switches, as a function of the first and second clock signals, connection of the flying capacitor between one state where the flying capacitor is connected between an input node and a switching node, and another state where the capacitor is connected between the switching node and a ground node. The duty cycle of the first/second clock signal varies so that when the flying capacitor voltage is lower than a target voltage a duration of the one state is increased, and when the flying capacitor voltage is higher than the target voltage a duration of the another state is increased.

Abstract: Circuitry for detecting a short across an inductor of a DC-DC converter includes a decoupling-circuit coupled between an inductor-terminal and an intermediate-node that, when activated, generates a detection-voltage (representative of voltage at the inductor-terminal) at the intermediate-node. A logic-circuit has an input coupled to the intermediate-node and an output generating a detection-signal. The detection-signal is asserted when the detection-voltage is closer to an input-voltage to the DC-DC converter than ground but is deasserted when the detection-voltage is closer to ground. Control-circuitry, at the beginning of a high-side conduction-phase, activates the decoupling-circuit and delays for a delay-period. After expiration of the delay-period and in response to the detection-signal being asserted, the control-circuitry completes the high-side conduction-phase.

Abstract: A DC-DC boost converter includes an input receiving an input voltage and an output producing an output voltage. A switching stage is formed by a low-side transistor arranged between a switching node and a ground node, and a high-side transistor arranged between the switching node and the output. The high-side transistor includes a body diode having an anode coupled to the switching node and a cathode coupled to the output. The converter is controlled in an asynchronous operation mode where the low-side transistor is driven alternately to a conductive state and a non-conductive state, and the high-side transistor is driven steadily to a non-conductive state. A variable load circuit is selectively coupled between the two output terminals when the converter is in the asynchronous operation mode in order to sink a load current having a value that is a function of a value of the input voltage.

Abstract: In a multi-level hybrid DC-DC converter with a flying capacitor, a feedback circuit includes a first oscillator and produces a first clock signal with a frequency dependent on an output voltage. A second oscillator produces a second clock signal having a frequency dependent on a reference voltage. A logic circuit switches, as a function of the first and second clock signals, connection of the flying capacitor between one state where the flying capacitor is connected between an input node and a switching node, and another state where the capacitor is connected between the switching node and a ground node. The duty cycle of the first/second clock signal varies so that when the flying capacitor voltage is lower than a target voltage a duration of the one state is increased, and when the flying capacitor voltage is higher than the target voltage a duration of the another state is increased.

Abstract: A supply node receives supply voltage and an output node provides a regulated output voltage to a load. A switching transistor is coupled between the supply and output nodes. The switching transistor is controlled by a drive signal generated by a control circuit to control switching activity. The control circuit includes circuitry to sense a feedback voltage indicative of the regulated output voltage and a comparator generating a comparison logic signal dependent on a comparison of the feedback voltage to a reference. A logic circuit generates a skip signal in response to the comparison logic signal. A counter generates a termination signal. Signal processing circuitry controls the switching activity by asserting the drive signal as a function of the skip signal and the termination signal.

Abstract: A time based boost DC-DC converter generates an output voltage using an inductor. A voltage error between the output voltage and a reference voltage is determined and processed in a) an integral control branch which converts the voltage error into an integral control current signal used to control a current controlled oscillator, and b) a proportional branch which converts the voltage error into a proportional control current signal used to control signal a delay line. Current flowing in the inductor is sensed, attenuated and used to apply adjustment to the integral and proportional control current signals. The output from the current controlled oscillator is passed through the delay line and phase detected in order to generate pulse width modulation (PWM) control signaling driving switch operation in the converter.

Abstract: A DC-DC converter circuit includes a switching stage with first and second switches, and a control circuit coupled to the switching stage. The control circuit detects a threshold for changing between a synchronous operation mode and an asynchronous operation mode, synchronizes the detected threshold with a beginning of a new switching cycle, applies feed-forward compensation at the beginning of an ON-time period to vary a duty cycle, and generates drive signals to control the switching stage.

Abstract: A non-inverting buck boost DC-DC converter operates with a ripple-hysteretic-current-mode-control including: a first state where control signals close a first high side switch and a second low side switch; a second state where control signals close the first high side switch and a second high side switch; a third state where control signals close a first low side switch and the second high side switch; and a fourth state where control signals close the first low side switch and the second low side switch. Control signal peak voltage and valley voltage are detected. Passing between the first, second, third and fourth states is dependent on peak voltage detection, valley voltage detection, expiration of a variable first time interval following entering the second state, and expiration of a fixed second time interval following entering the third state.

Abstract: An amplifier circuit includes a first input stage with a differential input transistor pair and a second gain stage having an output node coupled to a load. A node in the first gain stage is coupled to the output node in the second gain stage. A feedback line couples the output node to the control node of a first transistor of the differential input transistor pair. Current mirror circuitry is coupled to a current flow path through a further transistor in the second gain stage and includes a sensing node configured to produce a sensing signal indicative of the current supplied to the load. The sensing signal at the sensing node is directly fed back to the control node of the first transistor of the differential input transistor pair to provide a zero in the loop transfer function that is matched to and tracks and cancels out a load-dependent pole.

Abstract: A time-based DC-DC converter is controlled in response to a first oscillator signal based on a first control signal, a second oscillator signal based on a second control signal and a controlled current based on a feedback control signal. The first control signal and the second control signal are a function of the controlled current. The feedback control signal is generated as a function of the first and second oscillator signals by: generating at least two binary signals including a first binary signal based on a difference between the first oscillator signal and the reference signal and a second binary signal based on a difference between the second oscillator signal and the reference signal; and generating via a charge pump the feedback control signal based on the first binary signal and the second binary signal.

Abstract: A control circuit operates to control a switching stage of an electronic converter. The control circuit includes: first terminals providing drive signals to electronic switches of the switching stage; a second terminal receiving from a feedback circuit a first feedback signal proportional to a converter output voltage; and a third terminal configured to receive from a current sensor a second feedback signal proportional to an inductor current. A driver circuit provides the drive signals as a function of a PWM signal generated by a generator circuit as a function of the first and second feedback signals, a reference voltage and a slope compensation signal. A mode selection signal is generated as a function of a comparison between the input voltage and the output voltage. A feed-forward compensation circuit is configured to source and/or sink a compensation current as a function of a variation in the mode selection signal.