Abstract: A hybrid digital-to-analog converter including a charge-sharing digital-to-analog converter and a charge redistribution digital-to-analog converter is provided. The charge-sharing digital-to-analog converter is configured to receive a digital input signal having multiple bits. The bits include a most-significant-bit and a least-significant-bit. The charge-sharing digital-to-analog converter is configured to convert the most-significant-bit to provide a first portion of an analog signal and selectively share charges of first capacitors during a successive approximation of the most-significant-bit. The charge redistribution digital-to-analog converter is configured to convert the least-significant-bit to provide a second portion of the analog signal. The charge redistribution digital-to-analog converter performs charge redistribution by selectively connecting second capacitors to receive reference voltages during a successive approximation of the least-significant-bit.

Abstract: A hybrid digital-to-analog converter including a charge-sharing digital-to-analog converter and a charge redistribution digital-to-analog converter is provided. The charge-sharing digital-to-analog converter is configured to receive a digital input signal having multiple bits. The bits include a most-significant-bit and a least-significant-bit. The charge-sharing digital-to-analog converter is configured to convert the most-significant-bit to provide a first portion of an analog signal and selectively share charges of first capacitors during a successive approximation of the most-significant-bit. The charge redistribution digital-to-analog converter is configured to convert the least-significant-bit to provide a second portion of the analog signal. The charge redistribution digital-to-analog converter performs charge redistribution by selectively connecting second capacitors to receive reference voltages during a successive approximation of the least-significant-bit.

Abstract: An A/D converter including first and second A/D converters and a recombination module. The first A/D converter receives an analog input signal, converts the analog input signal to a first digital signal, and includes a successive approximation module, which performs a successive approximation to generate the first digital signal. The second A/D converter converts an analog output of the first A/D converter to a second digital signal. The analog output of the first A/D converter is generated based on the analog input signal. The second A/D converter is a fine conversion A/D converter relative to the first A/D converter. The second A/D converter performs the delta-sigma conversion process and includes a decimation filter that suppresses noise which reduces amplification and power consumption requirements of the first A/D converter and performs a delta-sigma decimation process to generate the second digital signal based on the analog output of the first A/D converter.

Abstract: A hybrid D/A converter is provided including first and second D/A converters. The first D/A converter receives a digital signal having an input voltage and converts a first most-significant-bit of the digital signal to be converted to an analog signal. The first D/A converter includes first capacitors, which are charged by the input voltage and reference voltages during a sampling phase of the digital signal. Charges of the first capacitors are shared during successive approximations of first bits of the digital input signal received by the hybrid D/A converter. The second D/A converter converts a first least-significant-bit of the digital input signal. The second D/A converter includes second capacitors, which are charged based on a common mode voltage during the sampling phase. The second D/A converter performs charge redistribution by connecting the second capacitors to receive the reference voltages during successive approximations of second bits of the digital signal.

Abstract: An A/D converter including a sample and hold circuit, first and second A/D converters and a combination circuit. The sample and hold circuit samples an analog input signal to generate bits. The first A/D converter generate a first digital signal based on the analog input signal and includes charge-sharing and charge-redistribution D/A converters that convert respectively a most-significant-bit and a first least significant bit. The first digital signal is generated based on outputs of the charge-sharing and charge redistribution D/A converters. The second A/D converter generates a second digital signal based on an output of the first A/D converter and includes a delta sigma D/A converter, which converts a second least significant bit. The second digital signal is generated based on an output of the delta sigma D/A converter. The second A/D converter is a fine conversion A/D converter relative to the first A/D converter.

Abstract: An A/D converter including a sample and hold circuit, first and second A/D converters and a combination circuit. The sample and hold circuit samples an analog input signal to generate bits. The first A/D converter generate a first digital signal based on the analog input signal and includes charge-sharing and charge-redistribution D/A converters that convert respectively a most-significant-bit and a first least significant bit. The first digital signal is generated based on outputs of the charge-sharing and charge redistribution D/A converters. The second A/D converter generates a second digital signal based on an output of the first A/D converter and includes a delta sigma D/A converter, which converts a second least significant bit. The second digital signal is generated based on an output of the delta sigma D/A converter. The second A/D converter is a fine conversion A/D converter relative to the first A/D converter.

Abstract: An A/D converter including first and second A/D converters and a recombination module. The first A/D converter receives an analog input signal, converts the analog input signal to a first digital signal, and includes a successive approximation module, which performs a successive approximation to generate the first digital signal. The second A/D converter converts an analog output of the first A/D converter to a second digital signal. The analog output of the first A/D converter is generated based on the analog input signal. The second A/D converter is a fine conversion A/D converter relative to the first A/D converter. The second A/D converter performs the delta-sigma conversion process and includes a decimation filter that suppresses noise which reduces amplification and power consumption requirements of the first A/D converter and performs a delta-sigma decimation process to generate the second digital signal based on the analog output of the first A/D converter.

Abstract: A hybrid D/A converter is provided including first and second D/A converters. The first D/A converter receives a digital signal having an input voltage and converts a first most-significant-bit of the digital signal to be converted to an analog signal. The first D/A converter includes first capacitors, which are charged by the input voltage and reference voltages during a sampling phase of the digital signal. Charges of the first capacitors are shared during successive approximations of first bits of the digital input signal received by the hybrid D/A converter. The second D/A converter converts a first least-significant-bit of the digital input signal. The second D/A converter includes second capacitors, which are charged based on a common mode voltage during the sampling phase. The second D/A converter performs charge redistribution by connecting the second capacitors to receive the reference voltages during successive approximations of second bits of the digital signal.

Abstract: A transducer for a storage medium has a supporting element positioned over the storage medium with a first head configured to interact with the storage medium and a second head operatively connected to the first head to interact with the storage medium. The second head is carried by the supporting element in a position adjacent to the first head, and the first head and the second head are aligned in a scanning direction. The first head performs the reading of a data item stored in a portion of the storage medium, the reading entailing the deletion of the data item, and the second head performs the rewriting of the data item in the same portion of the storage medium.

Abstract: A scrambling system for a digital-to-analog converter (DAC) includes a DAC that receives a digital input word and a scrambling module that randomly selects at least one of a plurality of current sources based on the digital input word. The DAC outputs an analog signal based on the at least one of the plurality of current sources.

Abstract: A transducer for a storage medium has a supporting element positioned over the storage medium with a first head configured to interact with the storage medium and a second head operatively connected to the first head to interact with the storage medium. The second head is carried by the supporting element in a position adjacent to the first head, and the first head and the second head are aligned in a scanning direction. The first head performs the reading of a data item stored in a portion of the storage medium, the reading entailing the deletion of the data item, and the second head performs the rewriting of the data item in the same portion of the storage medium.

Abstract: An analog-to-digital converter with a pipeline architecture for converting an analog input signal into a digital output signal with a predefined resolution includes a plurality of stages, each stage having a circuit for converting an analog local signal into a digital local signal with a local resolution lower than the predefined resolution, a circuit for determining an analog residue indicative of a quantization error of the converting circuit, a circuit for amplifying the analog residue by an inter-stage gain corresponding to the local resolution to generate the analog local signal for a next stage, and a circuit for combining the digital local signals of all the stages into the digital output signal weighting each digital local signal according to a digital weight depending on the corresponding inter-stage gain.

Abstract: An analog-to-digital converter (200) with a pipeline architecture for converting an analog input signal into a digital output signal with a predefined resolution is proposed. The converter includes a plurality of stages (1053-1050) each one having means (110, 115) for converting an analog local signal into a digital local signal with a local resolution lower than said resolution, means (120, 125) for determining an analog residue indicative of a quantization error of the means for converting, and means (130) for amplifying the analog residue by an inter-stage gain corresponding to the local resolution to generate the analog local signal for a next stage, and further includes means (204) for combining the digital local signals of all the stages into the digital output signal weighting each digital local signal according to a digital weight depending on the corresponding inter-stage gain.