Patents by Inventor Alessandro C. Callegari
Alessandro C. Callegari has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9099537Abstract: A method of selectively growing one or more carbon nano-tubes includes forming an insulating layer on a substrate, the insulating layer having a top surface; forming a via in the insulating layer; forming an active metal layer over the insulating layer, including sidewall and bottom surfaces of the via; and removing the active metal layer at portions of the top surface with an ion beam to enable the selective growth of one or more carbon nano-tubes inside the via.Type: GrantFiled: August 28, 2009Date of Patent: August 4, 2015Assignee: International Business Machines CorporationInventors: Katherina E. Babich, Alessandro C. Callegari, John J. Connolly, Eugene J. O'Sullivan
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Patent number: 8497212Abstract: Generally, the subject matter disclosed herein relates to modern sophisticated semiconductor devices and methods for forming the same, wherein a multilayer metal fill may be used to fill narrow openings formed in an interlayer dielectric layer. One illustrative method disclosed herein includes forming an opening in a dielectric material layer of a semiconductor device formed above a semiconductor substrate, the opening having sidewalls and a bottom surface. The method also includes forming a first layer of first fill material above the semiconductor device by forming the first layer inside the opening and at least above the sidewalls and the bottom surface of the opening.Type: GrantFiled: February 28, 2011Date of Patent: July 30, 2013Assignee: GLOBALFOUNDRIES Inc.Inventors: Katherina E. Babich, Alessandro C. Callegari, Christopher D. Sheraw, Eugene J. O'Sullivan
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Patent number: 8383483Abstract: The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits that each contains at least a first and a second gate stacks. The first gate stack is located over a first device region (e.g., an n-FET device region) in a semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer, a metallic gate conductor, and a silicon-containing gate conductor. The second gate stack is located over a second device region (e.g., a p-FET device region) in the semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer and a silicon-containing gate conductor. The first and second gate stacks can be formed over the semiconductor substrate in an integrated manner by various methods of the present invention.Type: GrantFiled: August 14, 2009Date of Patent: February 26, 2013Assignee: International Business Machines CorporationInventors: John C. Arnold, Glenn A. Biery, Alessandro C. Callegari, Tze-Chiang Chen, Michael P. Chudzik, Bruce B. Doris, Michael A. Gribelyuk, Young-Hee Kim, Barry P. Linder, Vijay Narayanan, Joseph S. Newbury, Vamsi K. Paruchuri, Michelle L. Steen
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Patent number: 8288237Abstract: A compound metal comprising TiC which is a p-type metal having a workfunction of about 4.75 to about 5.3, preferably about 5, eV that is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer is provided as well as a method of fabricating the TiC compound metal. Furthermore, the TiC metal compound of the present invention is a very efficient oxygen diffusion barrier at 1000° C. allowing very aggressive equivalent oxide thickness (EOT) and inversion layer thickness scaling below 14 ? in a p-metal oxide semiconductor (pMOS) device.Type: GrantFiled: August 14, 2009Date of Patent: October 16, 2012Assignee: International Business Machines CorporationInventors: Alessandro C. Callegari, Michael A. Gribelyuk, Dianne L. Lacey, Fenton R. Feeney, Katherine L. Saenger, Sufi Zafar
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Publication number: 20120217590Abstract: Generally, the subject matter disclosed herein relates to modern sophisticated semiconductor devices and methods for forming the same, wherein a multilayer metal fill may be used to fill narrow openings formed in an interlayer dielectric layer. One illustrative method disclosed herein includes forming an opening in a dielectric material layer of a semiconductor device formed above a semiconductor substrate, the opening having sidewalls and a bottom surface. The method also includes forming a first layer of first fill material above the semiconductor device by forming the first layer inside the opening and at least above the sidewalls and the bottom surface of the opening.Type: ApplicationFiled: February 28, 2011Publication date: August 30, 2012Applicant: GLOBALFOUNDRIES INC.Inventors: Katherina E. Babich, Alessandro C. Callegari, Christopher D. Sheraw, Eugene J. O'Sullivan
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Patent number: 8153514Abstract: The present invention provides a gate stack structure that has high mobilities and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.Type: GrantFiled: August 7, 2008Date of Patent: April 10, 2012Assignee: International Business Machines CorporationInventors: Wanda Andreoni, Alessandro C. Callegari, Eduard A. Cartier, Alessandro Curioni, Christopher P. D'Emic, Evgeni Gousev, Michael A. Gribelyuk, Paul C. Jamison, Rajarao Jammy, Dianne L. Lacey, Fenton R. McFeely, Vijay Narayanan, Carlo A. Pignedoli, Joseph F. Shepard, Jr., Sufi Zafar
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Publication number: 20110048930Abstract: A method of selectively growing one or more carbon nano-tubes includes forming an insulating layer on a substrate, the insulating layer having a top surface; forming a via in the insulating layer; forming an active metal layer over the insulating layer, including sidewall and bottom surfaces of the via; and removing the active metal layer at portions of the top surface with an ion beam to enable the selective growth of one or more carbon nano-tubes inside the via.Type: ApplicationFiled: August 28, 2009Publication date: March 3, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Katherina E. Babich, Alessandro C. Callegari, John J. Connolly, Eugene J. O'Sullivan
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Patent number: 7872317Abstract: A semiconductor structure including at least one n-type field effect transistor (nFET) and at least one p-type field effect transistor (pFET) that both include a metal gate having nFET behavior and pFET behavior, respectively, without including an upper polysilicon gate electrode is provided. The present invention also provides a method of fabricating such a semiconductor structure.Type: GrantFiled: July 23, 2009Date of Patent: January 18, 2011Assignee: International Business Machines CorporationInventors: Alessandro C. Callegari, Michael P. Chudzik, Bruce B. Doris, Vijay Narayanan, Vamsi K. Paruchuri, Michelle L. Steen
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Patent number: 7863083Abstract: A method for fabricating a CMOS gate electrode by using Re, Rh, Pt, Ir or Ru metal and a CMOS structure that contains such gate electrodes are described. The work functions of these metals make them compatible with current pFET requirements. For instance, the metal can withstand the high hydrogen pressures necessary to produce properly passivated interfaces without undergoing chemical changes. The thermal stability of the metal on dielectric layers such as SiO2, Al2O3 and other suitable dielectric materials makes it compatible with post-processing temperatures up to 1000° C. A low temperature/low pressure CVD technique with Re2(CO)10 as the source material is used when Re is to be deposited.Type: GrantFiled: August 25, 2008Date of Patent: January 4, 2011Assignee: International Business Machines CorporationInventors: Ricky Amos, Douglas A. Buchanan, Cyril Cabral, Jr., Alessandro C. Callegari, Supratik Guha, Hyungjun Kim, Fenton R. McFeely, Vijay Narayanan, Kenneth P. Rodbell, John J. Yurkas
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Patent number: 7833849Abstract: A method of fabricating semiconductor structure is provided in which at least one nFET device and a least one pFET device are formed on a semiconductor substrate. Each device region formed includes a dielectric stack that has a net dielectric constant equal to or greater than silicon dioxide. Gate stacks are provided on each of the dielectric stacks, wherein one of the gate stacks includes a metal gate electrode located atop a surface of a thinned polygate electrode.Type: GrantFiled: December 30, 2005Date of Patent: November 16, 2010Assignee: International Business Machines CorporationInventors: Alessandro C. Callegari, Tze-Chiang Chen, Michael P. Chudzik, Bruce B. Doris, Young-Hee Kim, Vijay Narayanan, Vamsi K. Paruchuri, Michelle L. Steen, Ying Zhang
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Patent number: 7776701Abstract: A compound metal comprising MOxNy which is a p-type metal having a workfunction of about 4.75 to about 5.3, preferably about 5, eV that is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer is provided as well as a method of fabricating the MOxNy compound metal. Furthermore, the MOxNy metal compound of the present invention is a very efficient oxygen diffusion barrier at 1000° C. allowing very aggressive equivalent oxide thickness (EOT) and inversion layer thickness scaling below 14 ? in a p-metal oxide semiconductor (pMOS) device. In the above formula, M is a metal selected from Group IVB, VB, VIB or VIIB of the Periodic Table of Elements, x is from about 5 to about 40 atomic % and y is from about 5 to about 40 atomic %.Type: GrantFiled: August 12, 2008Date of Patent: August 17, 2010Assignee: International Business Machines CorporationInventors: Alessandro C. Callegari, Michael A. Gribelyuk, Vijay Narayanan, Vamsi K. Paruchuri, Sufi Zafar
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Patent number: 7772016Abstract: Measurement of the extinction coefficient k is employed for effective and prompt in-line monitoring and/or controlling of the metal film composition. The dependency of the extinction coefficient on the composition of a metal compound is characterized by measuring the extinction coefficients of a series of the metal compound with different compositions. A monitor metal film is then deposited on a wafer. The extinction coefficient k of the film on the wafer is measured and a film compositional parameter is extracted. The wafer processing may continue if k is in specification or the needed compositional change in the film may be extracted from the measured value of the k and the established dependence of k on the composition of the film for out-of-spec k values.Type: GrantFiled: April 4, 2007Date of Patent: August 10, 2010Assignee: International Business Machines CorporationInventors: Russell D. Allen, Stephen L. Brown, Alessandro C. Callegari, Michael P. Chudzik, Vijay Narayanan, Vamsi K. Paruchuri
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Patent number: 7755159Abstract: A method of fabricating a dielectric film comprising atoms of Si, C, O and H (hereinafter SiCOH) that has improved insulating properties as compared with prior art dielectric films, including prior art SiCOH dielectric films that are not subjected to the inventive deep ultra-violet (DUV) is disclosed. The improved properties include reduced current leakage which is achieved without adversely affecting (increasing) the dielectric constant of the SiCOH dielectric film. In accordance with the present invention, a SiCOH dielectric film exhibiting reduced current leakage and improved reliability is obtained by subjecting an as deposited SiCOH dielectric film to a DUV laser anneal. The DUV laser anneal step of the present invention likely removes the weakly bonded C from the film, thus improving leakage current.Type: GrantFiled: June 2, 2008Date of Patent: July 13, 2010Assignee: International Business Machines CorporationInventors: Alessandro C. Callegari, Stephen A. Cohen, Fuad E. Doany
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Publication number: 20100044805Abstract: A multilayered gate stack having improved reliability (i.e., low charge trapping and gate leakage degradation) is provided. The inventive multilayered gate stack includes, from bottom to top, a metal nitrogen-containing layer located on a surface of a high-k gate dielectric and Si-containing conductor located directly on a surface of the metal nitrogen-containing layer. The improved reliability is achieved by utilizing a metal nitrogen-containing layer having a compositional ratio of metal to nitrogen of less than 1.1. The inventive gate stack can be useful as an element of a complementary metal oxide semiconductor (CMOS). The present invention also provides a method of fabricating such a gate stack in which the process conditions of a sputtering process are varied to control the ratio of metal and nitrogen within the sputter deposited layer.Type: ApplicationFiled: October 30, 2009Publication date: February 25, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alessandro C. Callegari, Michael P. Chudzik, Barry P. Linder, Renee T. Mo, Vijay Narayanan, Dae-Gyu Park, Vamsi K. Paruchuri, Sufi Zafar
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Patent number: 7667277Abstract: A compound metal comprising TiC which is a p-type metal having a workfunction of about 4.75 to about 5.3, preferably about 5, eV that is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer is provided as well as a method of fabricating the TiC compound metal. Furthermore, the TiC metal compound of the present invention is a very efficient oxygen diffusion barrier at 1000° C. allowing very aggressive equivalent oxide thickness (EOT) and inversion layer thickness scaling below 14 ? in a p-metal oxide semiconductor (pMOS) device.Type: GrantFiled: January 13, 2005Date of Patent: February 23, 2010Assignee: International Business Machines CorporationInventors: Alessandro C. Callegari, Michael A. Gribelyuk, Dianne L. Lacey, Fenton R. McFeely, Katherine L. Saenger, Sufi Zafar
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Publication number: 20100041221Abstract: The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits that each contains at least a first and a second gate stacks. The first gate stack is located over a first device region (e.g., an n-FET device region) in a semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer, a metallic gate conductor, and a silicon-containing gate conductor. The second gate stack is located over a second device region (e.g., a p-FET device region) in the semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer and a silicon-containing gate conductor. The first and second gate stacks can be formed over the semiconductor substrate in an integrated manner by various methods of the present invention.Type: ApplicationFiled: August 14, 2009Publication date: February 18, 2010Applicant: International Business Machines CoporationInventors: John C. Arnold, Glenn A. Biery, Alessandro C. Callegari, Tze-Chiang Chen, Michael P. Chudzik, Bruce B. Doris, Michael A. Gribelyuk, Young-Hee Kim, Barry P. Linder, Vijay Narayanan, Joseph S. Newbury, Vamsi K. Paruchuri, Michelle L. Steen
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Publication number: 20100015790Abstract: A compound metal comprising TiC which is a p-type metal having a workfunction of about 4.75 to about 5.3, preferably about 5, eV that is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer is provided as well as a method of fabricating the TiC compound metal. Furthermore, the TiC metal compound of the present invention is a very efficient oxygen diffusion barrier at 1000° C. allowing very aggressive equivalent oxide thickness (EOT) and inversion layer thickness scaling below 14 ? in a p-metal oxide semiconductor (pMOS) device.Type: ApplicationFiled: August 14, 2009Publication date: January 21, 2010Applicant: International Business Machines CorporationInventors: Alessandro C. Callegari, Michael A. Gribelyuk, Dianne L. Lacey, Fenton R. McFeely, Katherine L. Saenger, Sufi Zafar
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Publication number: 20090283830Abstract: A semiconductor structure including at least one n-type field effect transistor (nFET) and at least one p-type field effect transistor (pFET) that both include a metal gate having nFET behavior and pFET behavior, respectively, without including an upper polysilicon gate electrode is provided. The present invention also provides a method of fabricating such a semiconductor structure.Type: ApplicationFiled: July 23, 2009Publication date: November 19, 2009Applicant: International Business Machines CorporationInventors: Alessandro C. Callegari, Michael P. Chudzik, Bruce B. Doris, Vijay Narayanan, Vamsi K. Paruchuri, Michelle L. Steen
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Patent number: 7611979Abstract: A multilayered gate stack having improved reliability (i.e., low charge trapping and gate leakage degradation) is provided. The inventive multilayered gate stack includes, from bottom to top, a metal nitrogen-containing layer located on a surface of a high-k gate dielectric and Si-containing conductor located directly on a surface of the metal nitrogen-containing layer. The improved reliability is achieved by utilizing a metal nitrogen-containing layer having a compositional ratio of metal to nitrogen of less than 1.1. The inventive gate stack can be useful as an element of a complementary metal oxide semiconductor (CMOS). The present invention also provides a method of fabricating such a gate stack in which the process conditions of a sputtering process are varied to control the ratio of metal and nitrogen within the sputter deposited layer.Type: GrantFiled: February 12, 2007Date of Patent: November 3, 2009Assignee: International Business Machines CorporationInventors: Alessandro C. Callegari, Michael P. Chudzik, Barry P. Linder, Renee T. Mo, Vijay Narayanan, Dae-Gyu Park, Vamsi K. Paruchuri, Sufi Zafar
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Patent number: 7569466Abstract: A semiconductor structure including at least one n-type field effect transistor (nFET) and at least one p-type field effect transistor (pFET) that both include a metal gate having nFET behavior and pFET behavior, respectively, without including an upper polysilicon gate electrode is provided. The present invention also provides a method of fabricating such a semiconductor structure.Type: GrantFiled: December 16, 2005Date of Patent: August 4, 2009Assignee: International Business Machines CorporationInventors: Alessandro C. Callegari, Michael P. Chudzik, Bruce B. Doris, Vijay Narayanan, Vamsi K. Paruchuri, Michelle L. Steen