Patents by Inventor Alessandro Callegari
Alessandro Callegari has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8895352Abstract: Techniques for forming a thin coating of a material on a carbon-based material are provided. In one aspect, a method for forming a thin coating on a surface of a carbon-based material is provided. The method includes the following steps. An ultra thin silicon nucleation layer is deposited to a thickness of from about two angstroms to about 10 angstroms on at least a portion of the surface of the carbon-based material to facilitate nucleation of the coating on the surface of the carbon-based material. The thin coating is deposited to a thickness of from about two angstroms to about 100 angstroms over the ultra thin silicon layer to form the thin coating on the surface of the carbon-based material.Type: GrantFiled: June 2, 2009Date of Patent: November 25, 2014Assignee: International Business Machines CorporationInventors: Katherina Babich, Alessandro Callegari, Zhihong Chen, Edward Kiewra, Yanning Sun
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Patent number: 8816333Abstract: Techniques for forming a thin coating of a material on a carbon-based material are provided. In one aspect, a method for forming a thin coating on a surface of a carbon-based material is provided. The method includes the following steps. An ultra thin silicon nucleation layer is deposited to a thickness of from about two angstroms to about 10 angstroms on at least a portion of the surface of the carbon-based material to facilitate nucleation of the coating on the surface of the carbon-based material. The thin coating is deposited to a thickness of from about two angstroms to about 100 angstroms over the ultra thin silicon layer to form the thin coating on the surface of the carbon-based material.Type: GrantFiled: May 29, 2012Date of Patent: August 26, 2014Assignee: International Business Machines CorporationInventors: Katherina Babich, Alessandro Callegari, Zhihong Chen, Edward Kiewra, Yanning Sun
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Patent number: 8772116Abstract: A device and method for fabricating a capacitive component includes forming a high dielectric constant material over a semiconductor substrate and forming a scavenging layer on the high dielectric constant material. An anneal process forms oxide layer between the high dielectric constant layer and the scavenging layer such that oxygen in the high dielectric constant material is drawn out to reduce oxygen content.Type: GrantFiled: December 3, 2012Date of Patent: July 8, 2014Assignee: International Business Machines CorporationInventors: Alessandro Callegari, Ko-Tao Lee, Devendra K. Sadana, Kuen-Ting Shiu
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Publication number: 20140138781Abstract: A device and method for fabricating a capacitive component includes forming a high dielectric constant material over a semiconductor substrate and forming a scavenging layer on the high dielectric constant material. An anneal process forms oxide layer between the high dielectric constant layer and the scavenging layer such that oxygen in the high dielectric constant material is drawn out to reduce oxygen content.Type: ApplicationFiled: December 3, 2012Publication date: May 22, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alessandro CALLEGARI, Ko-Tao LEE, Devendra K. SADANA, Kuen-Ting SHIU
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Patent number: 8415677Abstract: A field effect transistor device and method which includes a semiconductor substrate, a dielectric gate layer, preferably a high dielectric constant gate layer, overlaying the semiconductor substrate and an electrically conductive oxygen barrier layer overlaying the gate dielectric layer. In one embodiment, there is a conductive layer between the gate dielectric layer and the oxygen barrier layer. In another embodiment, there is a low resistivity metal layer on the oxygen barrier layer.Type: GrantFiled: January 20, 2010Date of Patent: April 9, 2013Assignee: International Business Machines CorporationInventors: Praneet Adusumilli, Alessandro Callegari, Josephine B. Chang, Changhwan Choi, Martin Michael Frank, Michael A. Guillorn, Vijay Narayanan
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Publication number: 20120235119Abstract: Techniques for forming a thin coating of a material on a carbon-based material are provided. In one aspect, a method for forming a thin coating on a surface of a carbon-based material is provided. The method includes the following steps. An ultra thin silicon nucleation layer is deposited to a thickness of from about two angstroms to about 10 angstroms on at least a portion of the surface of the carbon-based material to facilitate nucleation of the coating on the surface of the carbon-based material. The thin coating is deposited to a thickness of from about two angstroms to about 100 angstroms over the ultra thin silicon layer to form the thin coating on the surface of the carbon-based material.Type: ApplicationFiled: May 29, 2012Publication date: September 20, 2012Applicant: International Business Machines CorporationInventors: Katherina Babich, Alessandro Callegari, Zhihong Chen, Edward Kiewra, Yanning Sun
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Publication number: 20110175147Abstract: A field effect transistor device and method which includes a semiconductor substrate, a dielectric gate layer, preferably a high dielectric constant gate layer, overlaying the semiconductor substrate and an electrically conductive oxygen barrier layer overlaying the gate dielectric layer. In one embodiment, there is a conductive layer between the gate dielectric layer and the oxygen barrier layer. In another embodiment, there is a low resistivity metal layer on the oxygen barrier layer.Type: ApplicationFiled: January 20, 2010Publication date: July 21, 2011Applicant: International Business Machines CorporationInventors: Praneet Adusumilli, Alessandro Callegari, Josephine B. Chang, Changhwan Choi, Martin M. Frank, Michael A. Guillorn, Vijay Narayanan
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Publication number: 20100301336Abstract: Techniques for forming a thin coating of a material on a carbon-based material are provided. In one aspect, a method for forming a thin coating on a surface of a carbon-based material is provided. The method includes the following steps. An ultra thin silicon nucleation layer is deposited to a thickness of from about two angstroms to about 10 angstroms on at least a portion of the surface of the carbon-based material to facilitate nucleation of the coating on the surface of the carbon-based material. The thin coating is deposited to a thickness of from about two angstroms to about 100 angstroms over the ultra thin silicon layer to form the thin coating on the surface of the carbon-based material.Type: ApplicationFiled: June 2, 2009Publication date: December 2, 2010Applicant: International Business Machines CorporationInventors: Katherina Babich, Alessandro Callegari, Zhihong Chen, Edward Kiewra, Yanning Sun
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Publication number: 20100296045Abstract: An eyewear assembly having a frame and a separable temple piece in which a digital memory device is at least partially held within a temple piece.Type: ApplicationFiled: October 1, 2008Publication date: November 25, 2010Applicant: Marchon Eyeware, Inc.Inventors: Giancarla Agnoli, Alberto Da Re, Alessandro Callegari
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Publication number: 20080038905Abstract: A compound metal comprising HfSiN which is a n-type metal having a workfunction of about 4.0 to about 4.5, preferably about 4.3, eV which is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer. Furthermore, after annealing the stack of HfSiN/high k dielectric/interfacial layer at a high temperature (on the order of about 1000° C.), there is a reduction of the interfacial layer, thus the gate stack produces a very small equivalent oxide thickness (12 ? classical), which cannot be achieved using TaSiN.Type: ApplicationFiled: October 19, 2007Publication date: February 14, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alessandro Callegari, Martin Frank, Rajarao Jammy, Dianne Lacey, Fenton McFeely, Sufi Zafar
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Publication number: 20070284698Abstract: A method of fabricating a dielectric film comprising atoms of Si, C, O and H (hereinafter SiCOH) that has improved insulating properties as compared with prior art dielectric films, including prior art SiCOH dielectric films that are not subjected to the inventive deep ultra-violet (DUV) is disclosed. The improved properties include reduced current leakage which is achieved without adversely affecting (increasing) the dielectric constant of the SiCOH dielectric film. In accordance with the present invention, a SiCOH dielectric film exhibiting reduced current leakage and improved reliability is obtained by subjecting an as deposited SiCOH dielectric film to a DUV laser anneal. The DUV laser anneal step of the present invention likely removes the weakly bonded C from the film, thus improving leakage current.Type: ApplicationFiled: March 29, 2007Publication date: December 13, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alessandro Callegari, Stephen Cohen, Fuad Doany
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Publication number: 20070152276Abstract: The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits that each contains at least a first and a second gate stacks. The first gate stack is located over a first device region (e.g., an n-FET device region) in a semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer, a metallic gate conductor, and a silicon-containing gate conductor. The second gate stack is located over a second device region (e.g., a p-FET device region) in the semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer and a silicon-containing gate conductor. The first and second gate stacks can be formed over the semiconductor substrate in an integrated manner by various methods of the present invention.Type: ApplicationFiled: December 30, 2005Publication date: July 5, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John Arnold, Glenn Biery, Alessandro Callegari, Tze-Chiang Chen, Michael Chudzik, Bruce Doris, Michael Gribelyuk, Young-Hee Kim, Barry Linder, Vijay Narayanan, Joseph Newbury, Vamsi Paruchuri, Michelle Steen
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Publication number: 20070152273Abstract: A semiconductor structure and a method of fabricating the same wherein the structure includes at least one nFET device and a least one pFET device, where at least one of the devices is a thinned Si-containing gated device and the other device is a metal gated device are provided. That is, a semiconductor structure is provided wherein at least one of the nFET or pFET devices includes a gate electrode stack comprising a thinned Si-containing electrode, i.e., polysilicon electrode, and an overlying first metal, while the other device includes a gate electrode stack that includes at least the first metal gate, without the thinned Si-containing electrode.Type: ApplicationFiled: December 30, 2005Publication date: July 5, 2007Applicant: INTERNATIONAL BUNISESS MACHINES CORPORATIONInventors: Alessandro Callegari, Tze-Chiang Chen, Michael Chudzik, Bruce Doris, Young-Hee Kim, Vijay Narayanan, Vamsi Paruchuri, Michelle Steen, Ying Zhang
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Patent number: 7235440Abstract: Ultra-thin oxide layers are formed utilizing low pressure processing to achieve self-limiting oxidation of substrates and provide ultra-thin oxide. The substrates to be processed can contain an initial dielectric layer such as an oxide layer, an oxynitride layer, a nitride layer, a high-k layer, or alternatively can lack an initial dielectric layer. The processing can be carried out using a batch type process chamber or, alternatively, using a single-wafer process chamber. One embodiment of the invention provides self-limiting oxidation of Si-substrates that results in SiO2 layers with a thickness of about 15 A, where the thickness of the SiO2 layers varies less than about 1 A over the substrates.Type: GrantFiled: July 31, 2003Date of Patent: June 26, 2007Assignees: Tokyo Electron Limited, International Business Machines CorporationInventors: David L O'Meara, Cory Wajda, Anthony Dip, Michael Toeller, Toshihara Furukawa, Kristen Scheer, Alessandro Callegari, Fred Buehrer, Sufi Zafar, Evgeni Gousev, Anthony Chou, Paul Higgins
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Publication number: 20070138578Abstract: A compound metal comprising MOxNy which is a p-type metal having a workfunction of about 4.75 to about 5.3, preferably about 5, eV that is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer is provided as well as a method of fabricating the MOxNy compound metal. Furthermore, the MOxNy metal compound of the present invention is a very efficient oxygen diffusion barrier at 1000° C. allowing very aggressive equivalent oxide thickness (EOT) and inversion layer thickness scaling below 14 ? in a p-metal oxide semiconductor (PMOS) device. In the above formula, M is a metal selected from Group IVB, VB, VIB or VIIB of the Periodic Table of Elements, x is from about 5 to about 40 atomic % and y is from about 5 to about 40 atomic %.Type: ApplicationFiled: December 19, 2005Publication date: June 21, 2007Applicant: International Business Machines CorporationInventors: Alessandro Callegari, Michael Gribelyuk, Vijay Narayanan, Vamsi Paruchuri, Sufi Zafar
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Publication number: 20070138563Abstract: A semiconductor structure including at least one n-type field effect transistor (nFET) and at least one p-type field effect transistor (pFET) that both include a metal gate having nFET behavior and pFET behavior, respectively, without including an upper polysilicon gate electrode is provided. The present invention also provides a method of fabricating such a semiconductor structure.Type: ApplicationFiled: December 16, 2005Publication date: June 21, 2007Applicant: International Business Machines CorporationInventors: Alessandro Callegari, Michael Chudzik, Bruce Doris, Vijay Narayanan, Vamsi Paruchuri, Michelle Steen
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Patent number: 7202186Abstract: Ultra-thin oxynitride layers are formed utilizing low-pressure processing to achieve self-limiting oxidation of substrates and provide ultra-thin oxynitride. The substrates to be processed can contain an initial dielectric layer such as an oxide layer, an oxynitride layer, or a nitride layer, or alternatively can lack an initial dielectric layer. The processing can be carried out using a batch type process chamber or a single-wafer process chamber.Type: GrantFiled: July 31, 2003Date of Patent: April 10, 2007Assignees: Tokyo Electron Limited, International Business Machines Corporation (IBM)Inventors: David L O'Meara, Cory Wajda, Anthony Dip, Michael Toeller, Toshihara Furukawa, Kristen Scheer, Alessandro Callegari, Fred Buehrer, Sufi Zafar, Evgeni Gousev, Anthony Chou, Paul Higgins
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Publication number: 20060289903Abstract: The present invention provides a gate stack structure that has high mobilites and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2/V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.Type: ApplicationFiled: August 30, 2006Publication date: December 28, 2006Inventors: Wanda Andreoni, Alessandro Callegari, Eduard Cartier, Alessandro Curioni, Christopher D'Emic, Evgeni Gousev, Michael Gribelyuk, Paul Jamison, Rajarao Jammy, Dianne Lacey, Fenton McFeely, Vijay Narayanan, Carlo Pignedoli, Joseph Shepard, Sufi Zafar
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Publication number: 20060163630Abstract: A compound metal comprising TiC which is a p-type metal having a workfunction of about 4.75 to about 5.3, preferably about 5, eV that is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer is provided as well as a method of fabricating the TiC compound metal. Furthermore, the TiC metal compound of the present invention is a very efficient oxygen diffusion barrier at 1000° C. allowing very aggressive equivalent oxide thickness (EOT) and inversion layer thickness scaling below 14 ? in a p-metal oxide semiconductor (pMOS) device.Type: ApplicationFiled: January 13, 2005Publication date: July 27, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alessandro Callegari, Michael Gribelyuk, Dianne Lacey, Fenton McFeely, Katherine Saenger, Sufi Zafar
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Publication number: 20060151846Abstract: A compound metal comprising HfSiN which is a n-type metal having a workfunction of about 4.0 to about 4.5, preferably about 4.3, eV which is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer. Furthermore, after annealing the stack of HfSiN/high k dielectric/interfacial layer at a high temperature (on the order of about 1000° C.), there is a reduction of the interfacial layer, thus the gate stack produces a very small equivalent oxide thickness (12 ? classical), which cannot be achieved using TaSiN.Type: ApplicationFiled: January 13, 2005Publication date: July 13, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alessandro Callegari, Martin Frank, Rajarao Jammy, Dianne Lacey, Fenton McFeely, Sufi Zafar