Patents by Inventor Alessandro Cevrero
Alessandro Cevrero has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11245638Abstract: A computer-implemented method of controlling communication resources and computation resources of a computerized system includes continually monitoring dual observables. The dual observables include one or more communication observables pertaining to one or more communication channels of the system, and one or more compute observables pertaining to a computational workload execution by a processor of the system. The method also includes jointly adjusting dual resources of the system based on the dual observables monitored, where the dual resources include communication resources for the one or more communication channels, and computation resources for the computational workload execution. Such a method can be used for sprinting both communication and computational resources, in a consistent way, for the system to best cope with temporary situations, in terms of both workload execution and data traffic. The invention is further directed to related systems and computer program products.Type: GrantFiled: February 15, 2019Date of Patent: February 8, 2022Assignee: International Business Machines CorporationInventors: Mitch Gusat, Yiyu Chen, Ilter Ozkaya, Alessandro Cevrero
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Publication number: 20200267091Abstract: A computer-implemented method of controlling communication resources and computation resources of a computerized system includes continually monitoring dual observables. The dual observables include one or more communication observables pertaining to one or more communication channels of the system, and one or more compute observables pertaining to a computational workload execution by a processor of the system. The method also includes jointly adjusting dual resources of the system based on the dual observables monitored, where the dual resources include communication resources for the one or more communication channels, and computation resources for the computational workload execution. Such a method can be used for sprinting both communication and computational resources, in a consistent way, for the system to best cope with temporary situations, in terms of both workload execution and data traffic. The invention is further directed to related systems and computer program products.Type: ApplicationFiled: February 15, 2019Publication date: August 20, 2020Inventors: Mitch Gusat, Yiyu Chen, Ilter Ozkaya, Alessandro Cevrero
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Patent number: 10720994Abstract: A system and method for a high-speed transmitter comprising a precoder configured to receive a sequence of input symbols and to generate for each received symbol a respective recoded symbol is disclosed. The transmitter includes a recoding unit configured for recoding each current received PAM-M based on the recoded symbol immediately preceding the current recoded symbol at the recoding unit, a shift unit configured for determining a shift value for each current received symbol from the recoding unit based on the symbol received from the recoding unit and immediately preceding the current symbol at the shift unit; and Feed-Forward Equalizer unit for applying the shift values to the respective symbols received from the recoding unit to generate a corresponding sequence of output symbols to be transmitted in an output stream.Type: GrantFiled: February 11, 2019Date of Patent: July 21, 2020Assignee: International Business Machines CorporationInventors: Alessandro Cevrero, Pier Andrea Francese, Marcel A. Kossel, Christian I. Menolfi, Ilter Özkaya, Thomas H. Toifl
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Patent number: 10673660Abstract: The present invention relates to a continuous time linear equalizer comprising a first signal path comprising a high pass filter and a first controllable transconductance unit and a second signal path comprising a second controllable transconductance unit. The continuous time linear equalizer comprises a summation node configured to receive complementary current summation signals of the first transconductance unit and the second transconductance unit. The high pass filter comprises a first port configured to receive an input signal, a second port coupled to a control port of the first transconductance unit and a third port coupled to the summation node. The invention is notably also directed to a corresponding method and a corresponding design structure.Type: GrantFiled: July 19, 2019Date of Patent: June 2, 2020Assignee: International Business Machines CorporationInventors: Pier Andrea Francese, Ilter Oezkaya, Alessandro Cevrero
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Patent number: 10516485Abstract: Devices and methods are provided to reduce the wake-up time of a Vertical Cavity Surface Emitting Laser (VCSEL) used in a data communication link. For example, in one aspect, a method for optical communications includes, in an optical communication device including a light-emitting device, applying a bias current to the light-emitting device and transmitting a pulse to the light-emitting device before transmitting a preamble signal or data signal to the light-emitting device, wherein the pulse has a voltage greater than a highest voltage of the preamble signal or data signal.Type: GrantFiled: December 14, 2018Date of Patent: December 24, 2019Assignee: International Business Machines CorporationInventors: Alessandro Cevrero, Daniel M. Kuchta, Christian I. Menolfi, Thomas E. Morf, Ilter Özkaya, Marc A. Seifried
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Publication number: 20190342128Abstract: The present invention relates to a continuous time linear equalizer comprising a first signal path comprising a high pass filter and a first controllable transconductance unit and a second signal path comprising a second controllable transconductance unit. The continuous time linear equalizer comprises a summation node configured to receive complementary current summation signals of the first transconductance unit and the second transconductance unit. The high pass filter comprises a first port configured to receive an input signal, a second port coupled to a control port of the first transconductance unit and a third port coupled to the summation node. The invention is notably also directed to a corresponding method and a corresponding design structure.Type: ApplicationFiled: July 19, 2019Publication date: November 7, 2019Inventors: Pier Andrea Francese, Ilter Oezkaya, Alessandro Cevrero
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Patent number: 10397027Abstract: The present invention relates to a continuous time linear equalizer comprising a first signal path comprising a high pass filter and a first controllable transconductance unit and a second signal path comprising a second controllable transconductance unit. The continuous time linear equalizer comprises a summation node configured to receive complementary current summation signals of the first transconductance unit and the second transconductance unit. The high pass filter comprises a first port configured to receive an input signal, a second port coupled to a control port of the first transconductance unit and a third port coupled to the summation node. The invention is notably also directed to a corresponding method and a corresponding design structure.Type: GrantFiled: September 26, 2017Date of Patent: August 27, 2019Assignee: International Business Machines CorporationInventors: Pier Andrea Francese, Ilter Oezkaya, Alessandro Cevrero
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Publication number: 20190173586Abstract: A system and method for a high-speed transmitter comprising a precoder configured to receive a sequence of input symbols and to generate for each received symbol a respective recoded symbol is disclosed. The transmitter includes a recoding unit configured for recoding each current received PAM-M based on the recoded symbol immediately preceding the current recoded symbol at the recoding unit, a shift unit configured for determining a shift value for each current received symbol from the recoding unit based on the symbol received from the recoding unit and immediately preceding the current symbol at the shift unit; and Feed-Forward Equalizer unit for applying the shift values to the respective symbols received from the recoding unit to generate a corresponding sequence of output symbols to be transmitted in an output stream.Type: ApplicationFiled: February 11, 2019Publication date: June 6, 2019Inventors: Alessandro Cevrero, Pier Andrea Francese, Marcel A. Kossel, Christian I. Menolfi, Ilter Özkaya, Thomas H. Toifl
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Publication number: 20190123830Abstract: Devices and methods are provided to reduce the wake-up time of a Vertical Cavity Surface Emitting Laser (VCSEL) used in a data communication link. For example, in one aspect, a method for optical communications includes, in an optical communication device including a light-emitting device, applying a bias current to the light-emitting device and transmitting a pulse to the light-emitting device before transmitting a preamble signal or data signal to the light-emitting device, wherein the pulse has a voltage greater than a highest voltage of the preamble signal or data signal.Type: ApplicationFiled: December 14, 2018Publication date: April 25, 2019Inventors: Alessandro Cevrero, Daniel M. Kuchta, Christian I. Menolfi, Thomas E. Morf, Ilter Özkaya, Marc A. Seifried
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Patent number: 10250332Abstract: Devices and methods are provided to reduce the wake-up time of a Vertical Cavity Surface Emitting Laser (VCSEL) used in a data communication link. For example, in one aspect, a method for optical communications includes, in an optical communication device including a light-emitting device, applying a bias current to the light-emitting device and transmitting a pulse to the light-emitting device before transmitting a preamble signal or data signal to the light-emitting device, wherein the pulse has a voltage greater than a highest voltage of the preamble signal or data signal.Type: GrantFiled: April 4, 2017Date of Patent: April 2, 2019Assignee: International Business Machines CorporationInventors: Alessandro Cevrero, Daniel M. Kuchta, Christian I. Menolfi, Thomas E. Morf, Ilter Özkaya, Marc A. Seifried
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Publication number: 20190097845Abstract: The present invention relates to a continuous time linear equalizer comprising a first signal path comprising a high pass filter and a first controllable transconductance unit and a second signal path comprising a second controllable transconductance unit. The continuous time linear equalizer comprises a summation node configured to receive complementary current summation signals of the first transconductance unit and the second transconductance unit. The high pass filter comprises a first port configured to receive an input signal, a second port coupled to a control port of the first transconductance unit and a third port coupled to the summation node. The invention is notably also directed to a corresponding method and a corresponding design structure.Type: ApplicationFiled: September 26, 2017Publication date: March 28, 2019Inventors: Pier Andrea Francese, Ilter Oezkaya, Alessandro Cevrero
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Patent number: 10236840Abstract: Embodiments describe a transadmittance amplifier comprising an inverting output port and a non-inverting output port. The transadmittance amplifier comprising a first differential transistor pair having a first transistor comprising an inverting input port. The first transistor is configured to provide an output current to the inverting output port. A second transistor comprising a non-inverting input port. The second transistor is configured to provide an output current to the non-inverting output port. A second differential transistor pair having a third transistor comprising an inverting input port and a fourth transistor comprising a non-inverting input port. A first current source and a second current source. The transadmittance amplifier comprises a first current mirror which is configured to mirror an output current of the fourth transistor to the inverting output port and a second current mirror which is configured to mirror an output current of the third transistor to the non-inverting output port.Type: GrantFiled: September 13, 2017Date of Patent: March 19, 2019Assignee: International Business Machines CorporationInventors: Alessandro Cevrero, Ilter Özkaya, Thomas H. Toifl
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Publication number: 20190081600Abstract: Embodiments describe a transadmittance amplifier comprising an inverting output port and a non-inverting output port. The transadmittance amplifier comprising a first differential transistor pair having a first transistor comprising an inverting input port. The first transistor is configured to provide an output current to the inverting output port. A second transistor comprising a non-inverting input port. The second transistor is configured to provide an output current to the non-inverting output port. A second differential transistor pair having a third transistor comprising an inverting input port and a fourth transistor comprising a non-inverting input port. A first current source and a second current source. The transadmittance amplifier comprises a first current mirror which is configured to mirror an output current of the fourth transistor to the inverting output port and a second current mirror which is configured to mirror an output current of the third transistor to the non-inverting output port.Type: ApplicationFiled: September 13, 2017Publication date: March 14, 2019Inventors: Alessandro Cevrero, Ilter Özkaya, Thomas H. Toifl
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Patent number: 10205525Abstract: A system and method for a high-speed transmitter comprising a precoder configured to receive a sequence of input symbols and to generate for each received symbol a respective recoded symbol is disclosed. The transmitter includes a recoding unit configured for recoding each current received PAM-M based on the recoded symbol immediately preceding the current recoded symbol at the recoding unit, a shift unit configured for determining a shift value for each current received symbol from the recoding unit based on the symbol received from the recoding unit and immediately preceding the current symbol at the shift unit; and Feed-Forward Equalizer unit for applying the shift values to the respective symbols received from the recoding unit to generate a corresponding sequence of output symbols to be transmitted in an output stream.Type: GrantFiled: November 30, 2017Date of Patent: February 12, 2019Assignee: International Business Machines CorporationInventors: Alessandro Cevrero, Pier Andrea Francese, Marcel A. Kossel, Christian I. Menolfi, Ilter Özkaya, Thomas H. Toifl
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Patent number: 10142090Abstract: Octagonal phase rotator apparatus is provided for producing an output signal that is phase dependent on a digital control code. The apparatus includes an I-mixer, a Q-mixer, and first and second IQ-mixers. The I-mixer is responsive to I-control bits of the digital control code. The Q-mixer is responsive to Q-control bits of the digital control code. The first and second IQ-mixers are respectively responsive to one or more IQ1-control bits and one or more IQ2-control bits of the digital control code. The I-mixer comprises an I-DAC for steering current between a positive phase IP and a negative phase IN of an in-phase (I) signal wherein the one or more I-control bits control switching of a first current unit between IP and IN, and a set of amplifiers for weighting the phases IP and IN, in dependence on current steered to each phase by the I-DAC, to produce a weighted I-signal.Type: GrantFiled: September 13, 2017Date of Patent: November 27, 2018Assignee: International Business Machines CorporationInventors: Alessandro Cevrero, Pier Andrea Francese, Ilter Özkaya, Thomas H. Toifl
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Publication number: 20180287707Abstract: Devices and methods are provided to reduce the wake-up time of a Vertical Cavity Surface Emitting Laser (VCSEL) used in a data communication link. For example, in one aspect, a method for optical communications includes, in an optical communication device including a light-emitting device, applying a bias current to the light-emitting device and transmitting a pulse to the light-emitting device before transmitting a preamble signal or data signal to the light-emitting device, wherein the pulse has a voltage greater than a highest voltage of the preamble signal or data signal.Type: ApplicationFiled: April 4, 2017Publication date: October 4, 2018Inventors: Alessandro Cevrero, Daniel M. Kuchta, Christian I. Menolfi, Thomas E. Morf, Ilter Özkaya, Marc A. Seifried
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Patent number: 8667046Abstract: A Generalized Programmable Counter Array (GPCA) is a reconfigurable multi-operand adder, which can be reprogrammed to sum a plurality of operands of arbitrary size. The GPCA is configured to compress the input words down to two operands using parallel counters. Resulting operands are then summed using a standard Ripple Carry Adder to produce the final result. The GPCA consists of a linear arrangement of identical compressor slices (CSlice).Type: GrantFiled: February 20, 2009Date of Patent: March 4, 2014Assignee: Ecole Polytechnique Federale de Lausanne/Service des Relations IndustriellesInventors: Philip Brisk, Alessandro Cevrero, Frank K. Gurkaynak, Paolo Ienne Lopez, Hadi Parandeh-Afshar
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Publication number: 20090216826Abstract: A Generalized Programmable Counter Array (GPCA) is a reconfigurable multi-operand adder, which can be reprogrammed to sum a plurality of operands of arbitrary size. The GPCA is configured to compress the input words down to two operands using parallel counters. Resulting operands are then summed using a standard Ripple Carry Adder to produce the final result. The GPCA consists of a linear arrangement of identical compressor slices (CSlice).Type: ApplicationFiled: February 20, 2009Publication date: August 27, 2009Applicant: Ecole Polytechnique Federale de Lausanne/ Service des Relations Industrielles(SRI)Inventors: Philip Brisk, Alessandro Cevrero, Frank K. Gurkaynak, Paolo Ienne Lopez, Hadi Parandeh-Afshar