Patents by Inventor Alessandro Cremonesi
Alessandro Cremonesi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230068500Abstract: A device includes a memory and processing circuitry coupled to the memory. The processing circuitry, in operation, generates an indication of a predicted difference in a direction of arrival (DoA) of a signal using a trained autoregressive model. A predicted indication of a DoA of the signal is generated based on a previous indication of the DoA of the signal and the indication of the predicted difference in the DoA of the signal. The processing circuitry actuates or controls an antenna array based on predicted indications of the DoA of the signal.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Inventors: Danilo Pietro PAU, Alessandro CREMONESI
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Patent number: 7254174Abstract: A process and a system is described for generating an MPEG output bitstream starting from an MPEG input bitstream. The output bitstream has a resolution modified with respect to the resolution of the input bitstream. In the input bitstream, first portions that substantially do not affect and second portions that do affect resolution variation are distinguished. The second portions are then subjected to a function of modification of the resolution obtained by filtering the second portions in a domain of the discrete cosine transform, and then are transferred to the output bitstream. A corresponding computer program product is also provided.Type: GrantFiled: February 11, 2002Date of Patent: August 7, 2007Assignee: STMicroelectronics S.r.l.Inventors: Danilo Pau, Daniele Alfonso, Fabrizio Basso, Emiliano Piccinelli, Alessandro Cremonesi
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Patent number: 7010041Abstract: In order to generate, starting from an input MPEG bitstream, an output MPEG bitstream having at least one entity chosen among syntax, resolution, and bitrate modified with respect to the input bitstream, first portions and second portions are distinguished in the input bitstream, which respectively substantially do not affect and do affect the variation in bitrate. When at least one between the syntax and the resolution is to be modified, the first portions of the input bitstream are subjected to the required translation, then transferring said first portions subjected to syntax and/or resolution translation to the output bitstream. When the resolution is left unaltered, the second portions are transferred from the input bitstream to the output bitstream in the substantial absence of processing operations. When the resolution is changed, the second portions of the input bitstream are subjected to a filtering in the domain of the discrete cosine transform.Type: GrantFiled: February 8, 2002Date of Patent: March 7, 2006Assignee: STMicroelectronics S.r.l.Inventors: Andrea Graziani, Luca Celetto, Daniele Alfonso, Fabrizio Basso, Alessandro Cremonesi, Danilo Pau
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Publication number: 20030145189Abstract: A processing architecture enables execution of one first set of instructions and one second set of instructions compiled for being executed by two different CPUs, the first set of instructions not being executable by the second CPU, and the second set of instructions not being executable by the first CPU. The architecture comprises a single CPU configured for executing both the instructions of the first set and the instructions of the second set. The single CPU in question being selectively switchable between a first operating mode, in which the single CPU executes the first set instructions, and a second operating mode, in which the single CPU executes the second set of instructions. The single processor is configured for recognizing a switching instruction between the first operating mode and the second operating mode and for switching between the first operating mode and the second operating mode according to the switching instruction.Type: ApplicationFiled: December 18, 2002Publication date: July 31, 2003Applicant: STMicroelectronics S.r.l.Inventors: Alessandro Cremonesi, Fabrizio Rovati, Danilo Pau
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Publication number: 20020186774Abstract: A process and a system is described for generating an MPEG output bitstream starting from an MPEG input bitstream. The output bitstream has a resolution modified with respect to the resolution of the input bitstream. -In the input bitstream, first portions that substantially do not affect and second portions that do affect resolution variation are distinguished. The second portions are then subjected to a function of modification of the resolution obtained by filtering the second portions in a domain of the discrete cosine transform, and then are transferred to the output bitstream. A corresponding computer program product is also provided.Type: ApplicationFiled: February 11, 2002Publication date: December 12, 2002Applicant: STMicroelectronics, S.r.I.Inventors: Danilo Pau, Daniele Alfonso, Fabrizio Basso, Emiliano Piccinelli, Alessandro Cremonesi
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Publication number: 20020159528Abstract: In order to generate, starting from an input MPEG bitstream, an output MPEG bitstream having at least one entity chosen among syntax, resolution, and bitrate modified with respect to the input bitstream, first portions and second portions are distinguished in the input bitstream, which respectively substantially do not affect and do affect the variation in bitrate. When at least one between the syntax and the resolution is to be modified, the first portions of the input bitstream are subjected to the required translation, then transferring said first portions subjected to syntax and/or resolution translation to the output bitstream. When the resolution is left unaltered, the second portions are transferred from the input bitstream to the output bitstream in the substantial absence of processing operations. When the resolution is changed, the second portions of the input bitstream are subjected to a filtering in the domain of the discrete cosine transform.Type: ApplicationFiled: February 8, 2002Publication date: October 31, 2002Applicant: STMicroelectronics, S.r.I.Inventors: Andrea Graziani, Luca Celetto, Daniele Alfonso, Fabrizio Basso, Alessandro Cremonesi, Danilo Pau
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Patent number: 5724395Abstract: A method of filtering digital signals having a high dynamic range includes splitting the sampled input signal into at least two portions addressing each of the portions to a respective program filter, and performing each filtering operation in parallel and independently, and reconstituting an output signal by summing together the digital outputs from each filter.Type: GrantFiled: January 28, 1994Date of Patent: March 3, 1998Assignee: SGS-Thomson Microelectronics S.r.l.Inventors: Carla Golla, Alessandro Cremonesi
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Patent number: 5710729Abstract: An oversampling digital filter with Finite Impulse Response is implemented using a serial structure having a memory for the coefficients, a memory for the signal samples to be filter, a multiplier connected to the output of the memories, an accumulator connected to the output of the multiplier, and a simple control unit which controls these elements according to an input clock signal.Type: GrantFiled: May 31, 1995Date of Patent: January 20, 1998Assignee: SGS-Thomson Microelectronics, S.r.l.Inventors: Sandro Delle Feste, Marco Bianchesi, Alessandro Cremonesi
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Patent number: 5594677Abstract: The input signal is filtered using at least two filtering operations (i.e. at least two types of transfer functions), and then is reconstituted by summing the two different digital outputs generated by each filtering arrangement, for example by using a summing circuit. In a preferred embodiment of the invention, a single programmable filter processor is used and is operated in two alternately selected modes, each sharing common filter coefficients. A clock signal alternately selects the two filtering modes. The subsequent outputs from a first mode are delayed and then added to the output of the second mode to produce the desired output signal.Type: GrantFiled: January 28, 1994Date of Patent: January 14, 1997Assignee: SGS-Thomson Microelectronics S.r.l.Inventors: Carla Golla, Alessandro Cremonesi
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Patent number: 5585794Abstract: An electronic device for the automatic conversion of sampling frequencies, being a type adapted to convert a predetermined frequency of a sampled input signal to a desired frequency of an output signal. The device is comprised of:a phase detector being input both the input frequency and the output frequency; a decoder block associated with the detector to determine an interpolation coefficient; an interpolation filter having a digital input for encoding the sampling signal and receiving the input frequency on the one side, and a digital signal representative of the interpolation coefficient on the other side; and a synchronizer connected after the filter and being input both said input and output frequencies, the synchronizer having a digital output for encoding the converted sampling signal.Type: GrantFiled: April 7, 1994Date of Patent: December 17, 1996Assignee: SGS-Thomson Microelectronics, S.r.l.Inventors: Fabrizio Airoldi, Alessandro Cremonesi
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Patent number: 5216506Abstract: A programmable device for storing digital video lines, being of a type intended for use in TV sets with digital frame scan features whereby a video line is sample coded in a digital signal, comprises at least one pair of memories each adapted to contain the code of one video line, and a bank of registers connected in series to one another and to each of the memories, at least one of the registers being fed, at its input terminals, with the digital signal to parallel the samples to be input to the memories.Type: GrantFiled: July 3, 1991Date of Patent: June 1, 1993Assignee: SGS Thomson Microelectronics S.R.L.Inventors: Fabrizio Airoldi, Franco Cavallotti, Alessandro Cremonesi, Gian G. Rizzotto
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Patent number: 5196935Abstract: The invention relates to a method for reducing noise of the pulsive type in digital video receiver sets. The method consists of picking up a noise-affected sample of a video signal and replacing it with a weighted average of samples located in the contour thereof; this allows the noise component to be fittered out with a lower load, in terms of circuit complexity, on the TV set.Type: GrantFiled: December 20, 1990Date of Patent: March 23, 1993Assignee: SGS-Thomson Microelectronics S.r.l.Inventors: Alessandro Cremonesi, Franco Cavallotti, Gianguido Rizzotto
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Patent number: 5103416Abstract: The digital filter includes a plurality of parallel adders, each whereof has a first input, a second input and an output; the parallel output of each adder is connected to the first input of the successive adder across a respective delay element. The second input of each adder is connected in parallel to the output of one of a plurality of memory banks, each whereof comprises a plurality of addressable memory cells, the addressing inputs whereof can be driven by a sampled digital signal to be filtered, and the memory cells of each bank contain a digital value which is equal to the product of a preset coefficient by the address of the cell itself.Type: GrantFiled: November 21, 1989Date of Patent: April 7, 1992Assignee: SGS-Thomson Microelectronics S.r.l.Inventors: Franco Cavallotti, Alessandro Cremonesi, Rinaldo Poluzzi
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Patent number: 5086299Abstract: A high conversion speed analog-to-digital converter is constituted by a plurality of comparison cells which in successive steps determine first the four most significant bits of the analog-to-digital conversion and then the least significant bits of the same, having first accomplished the reconversion of the four most significant bits to analog and their subsequent subtraction from the input signal.Type: GrantFiled: May 9, 1990Date of Patent: February 4, 1992Assignee: SGS-Thomson Microelectronics s.r.l.Inventors: Giulio Frigerio, Alessandro Cremonesi
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Patent number: 5053984Abstract: The filter includes an arithmetical chain of parallel adders alternated with delay elements, and a memory constituted by lines of one-bit cells. Each line is addressable by a decoder controlled by a digital signal to be filtered; each line of memory contains side by side values which correspond to the partial products of successive impulse-response coefficients for a value equal to the line address. The memory additionally includes a number of read amplifiers. The number of read amplifiers is equal to the number of cells of one line in order to read the bits of the addressed. The outputs of the amplifiers are connected to respective parallel inputs of the adders of the arithmetical chain. Each memory line contains these values in two's-complement binary form in words which decrease in length by one bit for each increment of 2 in the characteristic of the coefficients, starting from the one of lowest characteristic.Type: GrantFiled: November 21, 1989Date of Patent: October 1, 1991Assignee: SGS Thomson Microelectronics S.r.l.Inventors: Franco Cavallotti, Alessandro Cremonesi, Rinaldo Poluzzi
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Patent number: RE37440Abstract: The filter includes an arithmetical chain of parallel adders alternated with delay elements, and a memory constituted by lines of one-bit cells. Each line is addressable by a decoder controlled by a digital signal to be filtered; each line of memory contains side by side values which correspond to the partial products of successive impulse-response coefficients for a value equal to the line address. The memory additionally includes a number of read amplifiers. The number of read amplifiers is equal to the number of cells of one line in order to read the bits of the addressed. The outputs of the amplifiers are connected to respective parallel inputs of the adders of the arithmetical chain. Each memory line contains these values in two's-complement binary form in words which decrease in length by one bit for each increment of 2 in the characteristic of the coefficients, starting from the one of lowest characteristic.Type: GrantFiled: February 23, 1993Date of Patent: November 6, 2001Assignee: STMicroelectronics S.r.l.Inventors: Franco Cavallotti, Alessandro Cremonesi, Rinaldo Poluzzi
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Patent number: RE35472Abstract: A high conversion speed analog-to-digital converter is constituted by a plurality of comparison cells which in successive steps determine first the four most significant bits of the analog-to-digital conversion and then the least significant bits of the same, having first accomplished the reconversion of the four most significant bits to analog and their subsequent subtraction from the input signal.Type: GrantFiled: February 4, 1994Date of Patent: March 11, 1997Assignee: SGS-Thomson Microelectronics, S.r.l.Inventors: Giulio Frigerio, Alessandro Cremonesi
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Patent number: RE36026Abstract: A programmable device for storing digital video lines, being of a type intended for use in TV sets with digital frame scan features whereby a video line is sample coded in a digital signal, comprises at least one pair of memories each adapted to contain the code of one video line, and a bank of registers connected in series to one another and to each of the memories, at least one of the registers being fed, at its input terminals, with the digital signal to parallel the samples to be input to the memories.Type: GrantFiled: April 20, 1995Date of Patent: January 5, 1999Assignee: STMicroelectronics S.r.l.Inventors: Fabrizio Airoldi, Franco Cavallotti, Alessandro Cremonesi, Gian G. Rizzotto