Patents by Inventor ALESSANDRO D. GEIST

ALESSANDRO D. GEIST has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11109485
    Abstract: The present invention relates to a single board computer system with an improved memory and layout. The unique layout of the printed circuit board of the present invention allows for different parts to be placed in a back-to-back configuration to minimize the dimensions of the printed circuit board. This includes a high-performance radiation-hardened reconfigurable FPGA, for processing computation-intensive space systems, disposed on both sides of the printed circuit board. Four dual double data rate synchronous dynamic random-access memories (DDR2 SDRAMs) disposed on both the top side and on the bottom side of the printed circuit board reduce an operating voltage of said printed circuit board. A layout stack-up of the printed circuit board includes twenty-two symmetrical layers including ten ground layers, four power layers, six signal layers, a top layer, and a bottom layer.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: August 31, 2021
    Assignee: United States of America as represented by the Administrator of NASA
    Inventors: David J. Petrick, Alessandro D. Geist, Thomas P. Flatley
  • Patent number: 10667398
    Abstract: The present invention relates to a single board computer system with an improved memory and layout. The unique layout of the printed circuit board of the present invention allows for different parts to be placed in a back-to-back configuration to minimize the dimensions of the printed circuit board. This includes a high-performance radiation-hardened reconfigurable FPGA, for processing computation-intensive space systems, disposed on both sides of the printed circuit board. Four dual double data rate synchronous dynamic random-access memories (DDR2 SDRAMs) disposed on both the top side and on the bottom side of the printed circuit board reduce an operating voltage of said printed circuit board. A layout stack-up of the printed circuit board includes twenty-two symmetrical layers including ten ground layers, four power layers, six signal layers, a top layer, and a bottom layer.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: May 26, 2020
    Assignee: United States of America as represented by the Administrator of NASA
    Inventors: David J. Petrick, Alessandro D. Geist, Thomas P. Flatley
  • Publication number: 20170024298
    Abstract: Apparatus for in-system emulation of a target non-volatile memory device, such as a target PROM that stores FPGA configuration files and general data. The in-system emulation apparatus serves as stand-in hardware for the target PROM within the target system, mounted within a surface mount footprint and within volume constraints of the target PROM in the target system. The apparatus for in-system PROM emulation includes a device converter, and a surface mount emulator foot. The device converter includes at least one reprogrammable memory device, which stores developmental data that emulates data stored by the target PROM. The device converter includes a device converter circuit board, secured to the surface mount emulator foot. The device converter may include four Flash PROM reprogrammable devices, mounted above and below the device converter circuit board. The surface mount emulator foot includes an emulator foot circuit board, and a surface mount package emulation adapter.
    Type: Application
    Filed: July 24, 2015
    Publication date: January 26, 2017
    Inventors: ALESSANDRO D. GEIST, David J. Petrick