Abstract: Apparatus and methods are disclosed for performing block floating-point (BFP) operations, including in implementations of neural networks. All or a portion of one or more matrices or vectors can share one or more common exponents. Techniques are disclosed for selecting the shared common exponents. In some examples of the disclosed technology, a method includes producing BFP representations of matrices or vectors, at least two elements of the respective matrices or vectors sharing a common exponent, performing a mathematical operation on two or more of the plurality of matrices or vectors, and producing an output matrix or vector. Based on the output matrix or vector, one or more updated common exponents are selected, and an updated matrix or vector is produced having some elements that share the updated common exponents.

Abstract: Apparatus and methods are disclosed for performing block floating-point (BFP) operations, including in implementations of neural networks. All or a portion of one or more matrices or vectors can share one or more common exponents. Techniques are disclosed for selecting the shared common exponents. In some examples of the disclosed technology, a method includes producing BFP representations of matrices or vectors, at least two elements of the respective matrices or vectors sharing a common exponent, performing a mathematical operation on two or more of the plurality of matrices or vectors, and producing an output matrix or vector. Based on the output matrix or vector, one or more updated common exponents are selected, and an updated matrix or vector is produced having some elements that share the updated common exponents.

Abstract: Apparatus and methods are disclosed for performing block floating-point (BFP) operations, including in implementations of neural networks. All or a portion of one or more matrices or vectors can share one or more common exponents. Techniques are disclosed for selecting the shared common exponents. In some examples of the disclosed technology, a method includes producing BFP representations of matrices or vectors, at least two elements of the respective matrices or vectors sharing a common exponent, performing a mathematical operation on two or more of the plurality of matrices or vectors, and producing an output matrix or vector. Based on the output matrix or vector, one or more updated common exponents are selected, and an updated matrix or vector is produced having some elements that share the updated common exponents.

Abstract: Technology related to hardware accelerated neural network subgraphs is disclosed. In one example of the disclosed technology, a method includes receiving source code specifying a neural network model. The source code includes an application programming interface (API) marking a subgraph of the neural network model as targeted for hardware acceleration. The method includes compiling the subgraph to the neural network accelerator target to generate configuration information for the hardware accelerator. The method includes configuring the hardware accelerator to evaluate the neural network model, where the hardware accelerator is configured using the configuration information.

Abstract: Apparatus and methods are disclosed for performing block floating-point (BFP) operations, including in implementations of neural networks. All or a portion of one or more matrices or vectors can share one or more common exponents. Techniques are disclosed for selecting the shared common exponents. In some examples of the disclosed technology, a method includes producing BFP representations of matrices or vectors, at least two elements of the respective matrices or vectors sharing a common exponent, performing a mathematical operation on two or more of the plurality of matrices or vectors, and producing an output matrix or vector. Based on the output matrix or vector, one or more updated common exponents are selected, and an updated matrix or vector is produced having some elements that share the updated common exponents.

Abstract: A computing device for use in decision tree computation is provided. The computing device may include a software program executed by a processor using portions of memory of the computing device, the software program being configured to receive user input from a user input device associated with the computing device, and in response, to perform a decision tree task. The computing device may further include a decision tree computation device implemented in hardware as a logic circuit distinct from the processor, and which is linked to the processor by a communications interface. The decision tree computation device may be configured to receive an instruction to perform a decision tree computation associated with the decision tree task from the software program, process the instruction, and return a result to the software program via the communication interface.

Abstract: An intrusion detection system disclosed herein includes a detector circuit that measures a change in value of impedance of an interconnection circuitry. A decoder coupled to the detector decodes the measured value of the change in the impedance of the interconnection circuitry to determine existence of an abnormal condition. In an example implementation of the intrusion detection system, the change in the value of the impedance of the interconnection circuitry is represented by a change in the phase delay on the interconnection circuitry. An implementation of the intrusion detection circuit terminates communication using the interconnection circuitry upon detection of the abnormal condition. The intrusion detection system is further configured to interpret the abnormal condition as a communication signal to the interconnection circuitry.

Abstract: A set of population data that includes a plurality of individual population data entities is obtained. Each of the individual population data entities in the obtained set is streamed to an array of a plurality of evaluation functions. The evaluation functions are configured to evaluate each entity to determine an acceptability of the entity for a current state of a candidate centroid value associated with the evaluation function. Acceptance of input data entities is terminated after a first accepting one of the evaluation functions accepts an entity, based on the determined acceptability and on a predetermined priority ordering of acceptance. The first accepting one of the evaluation functions, in the priority ordering, incorporates population data associated with the accepted entity into an aggregator that is local to the first accepting evaluation function.

Abstract: A computing device for use in decision tree computation is provided. The computing device may include a software program executed by a processor using portions of memory of the computing device, the software program being configured to receive user input from a user input device associated with the computing device, and in response, to perform a decision tree task. The computing device may further include a decision tree computation device implemented in hardware as a logic circuit distinct from the processor, and which is linked to the processor by a communications interface. The decision tree computation device may be configured to receive an instruction to perform a decision tree computation associated with the decision tree task from the software program, process the instruction, and return a result to the software program via the communication interface.

Abstract: A method of producing an executable image from an object file without shared library support from the operating system, wherein the executable image requires a shared library file in order to resolve at least one of the symbols called for in the object file. A method of optimizing the loading of a previously linked file into working memory in a computer for executing in a single address space of the working memory, the file containing an instruction to make an indirect jump to a location in a shared library through an import section of the file. A method for optimizing the loading of a previously linked file into working memory in a computer for executing in a single address space of the working memory, the file containing plural sections with number-filled padding between the end of each section and a succeeding page boundary. A method of optimizing the loading of a previously linked file into working memory in a computer for executing in a memory sharable with other executables.

Abstract: An intrusion detection system disclosed herein includes a detector circuit that measures a change in value of impedance of an interconnection circuitry. A decoder coupled to the detector decodes the measured value of the change in the impedance of the interconnection circuitry to determine existence of an abnormal condition. In an example implementation of the intrusion detection system, the change in the value of the impedance of the interconnection circuitry is represented by a change in the phase delay on the interconnection circuitry. An implementation of the intrusion detection circuit terminates communication using the interconnection circuitry upon detection of the abnormal condition. The intrusion detection system is further configured to interpret the abnormal condition as a communication signal to the interconnection circuitry.

Abstract: A side channel communications system disclosed herein includes a receiver device with an internal circuitry where the operational speed of the internal circuitry changes in response to an external signal. When the receiver device receives an external signal, the operational speed of the internal circuitry changes. A detector detects the change in the operational speed of the internal circuitry to generate an output value, which is decoded to determine the information communicated by the external signal. In one implementation of the side channel communications system, the external transmitter communicates the external signal in the form of a temperature signal. Alternatively, the external transmitter communicates the external signal in the form of a change in the supply voltage.

Abstract: A method of producing an executable image from an object file without shared library support from the operating system, wherein the executable image requires a shared library file in order to resolve at least one of the symbols called for in the object file. A method of optimizing the loading of a previously linked file into working memory in a computer for executing in a single address space of the working memory, the file containing an instruction to make an indirect jump to a location in a shared library through an import section of the file. A method for optimizing the loading of a previously linked file into working memory in a computer for executing in a single address space of the working memory, the file containing plural sections with number-filled padding between the end of each section and a succeeding page boundary. A method of optimizing the loading of a previously linked file into working memory in a computer for executing in a memory sharable with other executables.

Abstract: Described is microprocessor architecture that includes at least one reconfigurable execution path (e.g., implemented via FPGAs or CPLDs). When an instruction is fetched, a mechanism determines whether the reconfigurable execution path (and/or which path) will handle that instruction. A content addressable memory may be used to determine the execution path when fed the instruction's operational code, or an arbiter and multiplexer may resolve conflicts if multiple instruction decode blocks recognize the same instruction. The execution path may be dynamically reconfigured, activated or deactivated as needed, such as to extend an instruction set, to optimize instructions for a particular application program, to implement a peripheral device, to provide parallel computing, and/or based on power consumption and/or processing power needs. Security may be provided by having the reconfigurable execution path loaded from an extension file that is associated with metadata, including security information.

Abstract: Logic and state information suitable for execution on a programmable hardware device may be generated from a task, such as evaluating a regular expression against a corpus. Hardware capacity requirements of the logic and state information on the programmable hardware device may be estimated. Once estimated, a plurality of the logic and state information generated from a plurality of tasks may be distributed into sets such that the logic and state information of each set fits within the hardware capacity of the programmable hardware device. The tasks within each set may be configured to execute in parallel on the programmable hardware device. Sets may then be executed in series, permitting virtualization of the resources.

Abstract: A post-compilation tool can rewrite executable images produced by a compiler. The tool can add extension definitions, insert extension-trigger instructions, and add a security signature. Operating system software may be notified of extension capabilities when loading the executable image, and may proceed to load an appropriate processor extension. The operating system software can manage availability of processor extensions on behalf of the applications.

Abstract: The present invention is directed to a loadable virtual memory manager, and generally to a computer operating system capable of supporting application programs running in a computer having a working memory, the computer operating system including a kernel resident in the working memory at run time, and a loadable virtual memory manager resident at link time outside of the working memory and dynamically loadable into the working memory at run time upon demand of one of the application programs. The kernel includes a loader for loading the virtual memory manager into the working memory in response to a demand from one of the application programs. The computer is able to access a storage memory separate from the working memory, the loadable virtual memory manager residing at link time in the storage memory. The loader loads the virtual memory manager from the storage memory to the working memory.

Abstract: A method of producing an executable image from an object file without shared library support from the operating system, wherein the executable image requires a shared library file in order to resolve at least one of the symbols called for in the object file. A method of optimizing the loading of a previously linked file into working memory in a computer for executing in a single address space of the working memory, the file containing an instruction to make an indirect jump to a location in a shared library through an import section of the file. A method for optimizing the loading of a previously linked file into working memory in a computer for executing in a single address space of the working memory, the file containing plural sections with number-filled padding between the end of each section and a succeeding page boundary. A method of optimizing the loading of a previously linked file into working memory in a computer for executing in a memory sharable with other executables.

Abstract: Described is microprocessor architecture that includes at least one reconfigurable execution path (e.g., implemented via FPGAs or CPLDs). When an instruction is fetched, a mechanism determines whether the reconfigurable execution path (and/or which path) will handle that instruction. A content addressable memory may be used to determine the execution path when fed the instruction's operational code, or an arbiter and multiplexer may resolve conflicts if multiple instruction decode blocks recognize the same instruction. The execution path may be dynamically reconfigured, activated or deactivated as needed, such as to extend an instruction set, to optimize instructions for a particular application program, to implement a peripheral device, to provide parallel computing, and/or based on power consumption and/or processing power needs. Security may be provided by having the reconfigurable execution path loaded from an extension file that is associated with metadata, including security information.

Abstract: Methods of optimizing the loading of a previously linked file into working memory in a computer for executing in a memory sharable with other executables, and converting an image which has been previously linked for executing in an unshared memory into an image optimized for use with virtual memory.