Abstract: A power MOS stage includes a first power MOS device and a second power MOS devices connected in parallel between a first node and a second node, the first power MOS device having a first voltage rating and the second power MOS device having a second voltage rating that is lower than the first voltage rating. A driver circuit is configured to drive control nodes of the first and second power MOS devices in a sequential manner when actuating the power MOS stage by actuating the first power MOS device before actuating the second power MOS device. The control nodes of the first and second power MOS devices are further driven in a sequential manner when deactuating the power MOS stage by deactuating the second power MOS device before deactuating the first power MOS device.

Abstract: A switching converter includes a voltage conversion circuit providing an output voltage from an input voltage and a PWM voltage generated in response to first and second oscillating voltages. The input stage of a transconductor circuit provides an input reference current following a difference between a reference voltage and a voltage dependent on the output voltage and according to a transconductance, and an output stage for providing an output reference current from the input reference current. A phase shifter shifts an oscillating reference voltage according to the output reference current to obtain the first and second oscillating voltages. The transconductance is controlled in response to the input voltage resulting in a change of the input reference current. Compensation for that change is provided by subtracting a variable compensation current from the input reference current, where the variable compensation current is generated in response to the input voltage.

Abstract: A DC-DC converter includes clock generation circuitry generating first and second clock signals that are out of phase, and a control signal generator generating a switching control signal at an edge of the second clock signal based upon a comparison of an error voltage to a summed voltage. Boost circuitry charges an energy storage component during an on-phase and discharges the energy storage component during an off-phase to thereby generate an output voltage. The on-phase and off-phase are set as a function of the switching control signal. Sum voltage generation circuitry generates a ramp voltage in response to an edge of the first clock signal and generates the summed voltage at an edge of the second clock signal. The sum voltage represents a sum of the ramp voltage and a voltage representative of the current flowing in the energy storage component during the on-phase.

Abstract: First and second n-channel FETs are connected in series between first and second terminals with an intermediate switching node. First and second driver circuits drive gates of the first and second n-channel FETs, respectively, in response to drive signals. The first driver circuit does not implement slew-rate control. A first resistor and capacitor are connected in series between the output of the first driver circuit and an intermediate node. A first electronic switch is connected between the intermediate node and the first terminal. A second electronic switch is connected between the intermediate node and the gate terminal of the first n-channel FET. A second resistor and a third electronic switch are connected in series between the gate terminal of the first n-channel FET and the switching node. A control circuit generates the drive signals and a first, second and third control signal for the first, second and third electronic switch.

Abstract: A half-bridge converter is controlled by a circuit including a differential circuit receiving a reference signal and a feedback signal which is a function of an output signal from the converter. The half-bridge converter includes high-side and low-side electronic switches. A comparator generates a PWM-modulated signal for controlling the converter as a function of the duty cycle of the PWM-modulated signal in response to a signal at an intermediate node between the high-side and low-side electronic switches and an output of the differential circuit. A gain circuit block coupled between the intermediate node and the input of the comparator applies a ramp signal to the input of the comparator which is a function of the signal at the intermediate node. A variable gain is applied by the gain circuit block in order to keep a constant value for the duty cycle of said PWM-modulated signal irrespective of converter operation.

Abstract: The present invention is a system for assembling panoramic images of a scene captured by a panoramic image capture device having a decoding unit configured to read image content data from the image capture device, an information reading unit configured to extract device parameters about the capture device, and an image processing unit configured to assemble an output image using the image content data and the device parameters.

Abstract: A power MOS stage includes a first power MOS device and a second power MOS devices connected in parallel between a first node and a second node, the first power MOS device having a first voltage rating and the second power MOS device having a second voltage rating that is lower than the first voltage rating. A driver circuit is configured to drive control nodes of the first and second power MOS devices in a sequential manner when actuating the power MOS stage by actuating the first power MOS device before actuating the second power MOS device. The control nodes of the first and second power MOS devices are further driven in a sequential manner when deactuating the power MOS stage by deactuating the second power MOS device before deactuating the first power MOS device.

Abstract: A DC-DC converter includes clock generation circuitry generating first and second clock signals that are out of phase, and a control signal generator generating a switching control signal at an edge of the second clock signal based upon a comparison of an error voltage to a summed voltage. Boost circuitry charges an energy storage component during an on-phase and discharges the energy storage component during an off-phase to thereby generate an output voltage. The on-phase and off-phase are set as a function of the switching control signal. Sum voltage generation circuitry generates a ramp voltage in response to an edge of the first clock signal and generates the summed voltage at an edge of the second clock signal. The sum voltage represents a sum of the ramp voltage and a voltage representative of the current flowing in the energy storage component during the on-phase.

Abstract: A half-bridge converter is controlled by a circuit including a differential circuit receiving a reference signal and a feedback signal which is a function of an output signal from the converter. The half-bridge converter includes high-side and low-side electronic switches. A comparator generates a PWM-modulated signal for controlling the converter as a function of the duty cycle of the PWM-modulated signal in response to a signal at an intermediate node between the high-side and low-side electronic switches and an output of the differential circuit. A gain circuit block coupled between the intermediate node and the input of the comparator applies a ramp signal to the input of the comparator which is a function of the signal at the intermediate node. A variable gain is applied by the gain circuit block in order to keep a constant value for the duty cycle of said PWM-modulated signal irrespective of converter operation.

Abstract: First and second FETs of a half-bridge are series connected between first and second terminals and are gate driven, respectively, by first and second drivers. An inductance is connected to the intermediate node of the half-bridge. Power supply for the second driver circuit is a supply voltage generated by a voltage regulator as a function of the voltage between the first and the second terminal. Power supply for the first driver circuit is a supply voltage generated by a bootstrap capacitor having a first terminal connected via a first switch to receive the supply voltage output from the voltage regulator and a second terminal connected to the intermediate node. The first terminal of the bootstrap capacitor is further connected by a second switch to receive a second supply voltage. A control circuit generates control signals for the first and second driver circuits and the first and second switches.

Abstract: The present invention is a system for capturing and assembling panoramic image data having a panoramic image capture device with image assembly parameters and configured to capture image content data, an encoding device coupled to the panoramic image capture device and configured to combine the image content data and the image assembly parameters into a panoramic image file, and a decoding device configured to receive the panoramic image file and assemble, based on the image assembly parameters, at least a portion of the image content data into an output image.

Abstract: A switching amplifier, such as a Class D amplifier, includes a current sensing circuit. The current sensing circuit is formed by replica loop circuits that are selectively coupled to corresponding output inverter stages of the switching amplifier. The replica loop circuits operated to produce respective replica currents of the output currents generated by the output inverter stages. A sensing circuitry is coupled to receive the replica currents from the replica loop circuits and operates to produce an output sensing signal as a function of the respective replica currents.

Abstract: A switching amplifier, such as a Class D amplifier, includes a current sensing circuit. The current sensing circuit is formed by replica loop circuits that are selectively coupled to corresponding output inverter stages of the switching amplifier. The replica loop circuits operated to produce respective replica currents of the output currents generated by the output inverter stages. A sensing circuitry is coupled to receive the replica currents from the replica loop circuits and operates to produce an output sensing signal as a function of the respective replica currents.

Abstract: An auto-tuned ramp generator and a method for generating a sawtooth signal are provided. In the method and apparatus, a sawtooth signal is compared to a first reference voltage and a second reference voltage. In response to determining that the sawtooth signal does not exceed the first reference voltage, the voltage level of the sawtooth signal is increased. In response to determining that the sawtooth signal exceeds the second reference voltage, the voltage level of the sawtooth signal is decreased. The voltage level the sawtooth signal is retained if the sawtooth signal remains between the first and second reference voltages.

Abstract: A half-bridge converter is controlled by a circuit including a differential circuit receiving a reference signal and a feedback signal which is a function of an output signal from the converter. The half-bridge converter includes high-side and low-side electronic switches. A comparator generates a PWM-modulated signal for controlling the converter as a function of the duty cycle of the PWM-modulated signal in response to a signal at an intermediate node between the high-side and low-side electronic switches and an output of the differential circuit. A gain circuit block coupled between the intermediate node and the input of the comparator applies a ramp signal to the input of the comparator which is a function of the signal at the intermediate node. A variable gain is applied by the gain circuit block in order to keep a constant value for the duty cycle of said PWM-modulated signal irrespective of converter operation.

Abstract: A switching amplifier, such as a Class D amplifier, includes a current sensing circuit. The current sensing circuit is formed by replica loop circuits that are selectively coupled to corresponding output inverter stages of the switching amplifier. The replica loop circuits operated to produce respective replica currents of the output currents generated by the output inverter stages. A sensing circuitry is coupled to receive the replica currents from the replica loop circuits and operates to produce an output sensing signal as a function of the respective replica currents.

Abstract: An auto-tuned ramp generator and a method for generating a sawtooth signal are provided. In the method and apparatus, a sawtooth signal is compared to a first reference voltage and a second reference voltage. In response to determining that the sawtooth signal does not exceed the first reference voltage, the voltage level of the sawtooth signal is increased. In response to determining that the sawtooth signal exceeds the second reference voltage, the voltage level of the sawtooth signal is decreased. The voltage level the sawtooth signal is retained if the sawtooth signal remains between the first and second reference voltages.

Abstract: A circuit includes an input transistor pair with first and second input transistors, the first input transistor having a control terminal configured to receive an input signal and a cascode transistor pair including a first and second cascode transistors having a common control node. A bias circuit has a bias input configured to receive the input signal and a first bias output coupled to the common node of the first and second cascode transistors. The bias circuit includes a signal tracking circuit operating to generate the first bias output to track the input signal. A pair of load transistors are coupled to the input transistor pair and biased by a second bias output of the bias circuit.

Abstract: A triangular-voltage generator has an input terminal that receives a power supply voltage and an output terminal that supplies a triangular-wave voltage having a repetition period. An operational amplifier in an integrator configuration has a first input, a second input and an output coupled to the output terminal. The second input receives a reference voltage as a function of the power supply voltage. The first input is selectively and alternately connected to the input terminal during a first half-period of the repetition period and to a reference terminal during a second half-period of the repetition period.

Abstract: An energy harvesting interface receives an electrical signal from an inductive transducer and outputs a supply signal. An input branch includes a first switch and a second switch connected in series between a first input terminal and an output terminal, and further a third switch and a fourth switch connected in series between a second input terminal and the output terminal. A first electrical-signal-detecting device coupled across the second switch detects a first threshold value of an electric storage current in the inductor of the transducer. A second electrical-signal-detecting device coupled across the fourth switch detects whether the electric supply current that flows through the fourth switch reaches a second threshold value lower than the first threshold value.