Abstract: Software and hardware for monitoring, testing, and developing communication and electronic systems on spacecrafts. Several systems are provided to monitor, test, and control a next generation SpaceCube, including a RadHard Monitor (RHM), a Mini ASTM Board, an FMC+ ASTM Board, a Mini Evaluation Board, a MEZZ and an Automated Test Suite. The RHM are FPGA IP and hardware configured to monitor COTS components. The Mini ASTM Board connects a Mini Processor Card to an ASTM for electrical testing. FMC+ ASTM Card connects FMC and FMC+ test cards to the ASTM for electrical testing. A Mini Evaluation Board supplies all necessary power to the Mini Processor card. The MEZZ is a multi-use GSE test board that is compatible with several different development platforms in the SpaceCube to allow developers to develop and test their software. The Automated Test Suite provides functional testing of an assembled SpaceCube board.

Abstract: The present invention relates to a single-board solid state data recorder (SSDR) card configured for use in a 1U CubeSat payload form-factor multi-purpose architecture, which includes: a field programmable gate array (FPGA): a plurality of NAND storage banks of non-volatile NAND Flash storage, the plurality of NAND storage banks which store operational data, each of which is controlled by a NAND Flash controller which controls the signaling of the plurality of NAND storage banks and reading and writing to the plurality of NAND storage banks; and a plurality of SpaceWire nodes and a plurality of multi-gigabit transceivers which command the SSDR card and read/write data to the SSDR card; wherein the plurality of NAND Flash memory banks is independently controlled and independently powered.

Abstract: The present invention relates to a single-board processor card configured for use in a 1U CubeSat payload form-factor multi-purpose architecture, including: a field-programmable-gate-array (FPGA) which is reconfigurable in flight; wherein a configuration memory of the FPGA can be scrubbed in flight to correct errors or upsets; and a radiation-hardened monitor (RHM) which provides radiation mitigation and system monitoring of the single-board processor card, and which reconfigures said FPGA during flight, scrubs the configuration memory, and monitors a health of the FPGA. The 1U CubeSat payload form-factor multi-purpose architecture includes a backplane having a plurality of slots, one of the plurality of slots which accommodates the single-board processor card, wherein the backplane routes signals to a plurality of standard-sized processor cards, interchangeably disposed in any of the plurality of slots.

Abstract: A single board computer system radiation hardened for space flight includes a printed circuit board having a top side and bottom side; a reconfigurable field programmable gate array (FPGA) processor device disposed on the top side; a connector disposed on the top side; a plurality of peripheral components mounted on the bottom side; and wherein a size of the single board computer system is not greater than approximately 7 cm×7 cm.

Abstract: A processing system including an FPGA having a dual port RAM and for use in hostile environments. The FPGA includes three portions: a C&DH portion; a first scratch pad portion receiving a first set of data, processing the first set of data, and outputting a first set of processed data to a first location of the RAM; and a second scratch pad portion receiving a second set of data identical to the first set of data, processing the second set of data in the same way that the first set of data is processed, and outputting a second set of processed data to a second location of the RAM. The C&DH portion compares the first set of processed data to the second set of processed data and, if the first set of processed data is the same as the second set of processed data, outputs one set of processed data.

Abstract: A processing system including an FPGA having a dual port RAM and for use in hostile environments. The FPGA includes three portions: a C&DH portion; a first scratch pad portion receiving a first set of data, processing the first set of data, and outputting a first set of processed data to a first location of the RAM; and a second scratch pad portion receiving a second set of data identical to the first set of data, processing the second set of data in the same way that the first set of data is processed, and outputting a second set of processed data to a second location of the RAM. The C&DH portion compares the first set of processed data to the second set of processed data and, if the first set of processed data is the same as the second set of processed data, outputs one set of processed data.

Abstract: A processing system having a small form factor and configured to connect to an external platform. The processing system includes input interfaces configured to receive an input signal to be processed; a radiation tolerant field programmable gate array including processors configured to process the input signal; memory containing reconfigurable instructions for the processors that, when the reconfigurable instructions are executed, process the input signal and obtain the output signal; output interfaces configured to send the output signal to the external platform; and a reset logic element configured to selectively reset the field programmable gate array and at least one of the processors in response to a reset command. The input interfaces include at least one gigabit Ethernet interface and at least one space-rated balanced voltage digital interface circuit.