Abstract: A device includes a local oscillator, an all-digital phase-locked loop, a digital signal generator, sampling circuitry, and an interface. The local oscillator generates a local clock signal. The all-digital phase locked loop generates a sampling control signal. The ADPLL includes a phase-error detector, a digital filter and a sigma-delta modulator. The phase detector generates a phase error signal based on a loop clock signal and a received reference signal. The digital filter generates a signal indicative of a frequency ratio between a frequency of the reference clock signal and the local clock frequency based on the phase error signal. The sigma-delta modulator generates a modulated signal based on the signal indicative of the frequency ratio. The sampling control signal is based on the modulated signal. The sampling circuitry samples digital signals generated by the digital signal generator at a sampling frequency, which is a function of the sampling control signal.

Abstract: The sensor is configured to provide a digital output signal and has a digital detector, which is configured to detect a physical quantity and generate a conditioned digital signal indicative of the detected physical quantity; and a rate modification stage, configured to receive the conditioned digital signal and a group of parameters, the group of parameters comprising an interpolation factor and a downsampling factor, and to provide the digital output signal. The rate modification stage has an interpolator and a decimation element. The interpolator is configured to receive and to upsample the conditioned digital signal based on the interpolation factor and to provide an interpolated signal. The decimation element is configured to downsample the interpolated signal based on the downsampling factor, thereby generating the digital output signal.

Abstract: A demodulator for demodulating the in-phase component of an input signal which is in-phase and quadrature modulated. The demodulator includes a register storing a phase calibration value and a temperature sensor that performs a plurality of temperature sensings. A compensating stage generates for each temperature sensed a corresponding first sample on the basis of the difference between the sensed temperature and a calibration temperature and a compensation function indicative of a relationship existing between the phase of the input signal and the temperature. A combination stage generates a plurality of second samples, each second sample being a function of the phase calibration value and a corresponding first sample. A generating stage generates a demodulating signal having a phase which depends on the second samples and a demodulating stage demodulates the input signal by means of the demodulating signal.

Abstract: A demodulator for demodulating the in-phase component of an input signal which is in-phase and quadrature modulated. The demodulator includes a register storing a phase calibration value and a temperature sensor that performs a plurality of temperature sensings. A compensating stage generates for each temperature sensed a corresponding first sample on the basis of the difference between the sensed temperature and a calibration temperature and a compensation function indicative of a relationship existing between the phase of the input signal and the temperature. A combination stage generates a plurality of second samples, each second sample being a function of the phase calibration value and a corresponding first sample. A generating stage generates a demodulating signal having a phase which depends on the second samples and a demodulating stage demodulates the input signal by means of the demodulating signal.

Abstract: A demodulator for demodulating the in-phase component of an input signal which is in-phase and quadrature modulated. The demodulator includes a register storing a phase calibration value and a temperature sensor that performs a plurality of temperature sensings. A compensating stage generates for each temperature sensed a corresponding first sample on the basis of the difference between the sensed temperature and a calibration temperature and a compensation function indicative of a relationship existing between the phase of the input signal and the temperature. A combination stage generates a plurality of second samples, each second sample being a function of the phase calibration value and a corresponding first sample. A generating stage generates a demodulating signal having a phase which depends on the second samples and a demodulating stage demodulates the input signal by means of the demodulating signal.

Abstract: A demodulator demodulates an in-phase component of an input signal which is in-phase and quadrature modulated. The demodulator includes a register storing a phase calibration value having an integer part and a fractional part. A noise-shaping modulator generates a succession of quantized values of integer type, the quantized values having a mean equal to the phase calibration value. A generating stage generates a demodulating signal phase locked with the input signal, the demodulating signal having a phase which depends linearly on the quantized values. A demodulating stage demodulates the input signal by means of the demodulating signal.

Abstract: A demodulator demodulates an in-phase component of an input signal which is in-phase and quadrature modulated. The demodulator includes a register storing a phase calibration value having an integer part and a fractional part. A noise-shaping modulator generates a succession of quantized values of integer type, the quantized values having a mean equal to the phase calibration value. A generating stage generates a demodulating signal phase locked with the input signal, the demodulating signal having a phase which depends linearly on the quantized values. A demodulating stage demodulates the input signal by means of the demodulating signal.

Abstract: A demodulator for demodulating the in-phase component of an input signal which is in-phase and quadrature modulated. The demodulator includes a register storing a phase calibration value and a temperature sensor that performs a plurality of temperature sensings. A compensating stage generates for each temperature sensed a corresponding first sample on the basis of the difference between the sensed temperature and a calibration temperature and a compensation function indicative of a relationship existing between the phase of the input signal and the temperature. A combination stage generates a plurality of second samples, each second sample being a function of the phase calibration value and a corresponding first sample. A generating stage generates a demodulating signal having a phase which depends on the second samples and a demodulating stage demodulates the input signal by means of the demodulating signal.

Abstract: The present disclosure refers to a digital microphone device providing a single-bit Pulse Density Modulation PDM output signal. The digital microphone comprises a microphone, arranged to convert an acoustic input signal into an analog electrical signal, and a preamplifier, having a variable gain, arranged to receive the analog electrical signal and to provide an amplified analog electrical signal, depending on the variable gain. The variable gain depends on a gain control signal. The digital microphone further comprises an Analog-to-Digital Converter block, arranged to receive the amplified analog electrical signal and to convert it into a respective digital signal; and a compensation block, arranged to receive the digital signal and to perform a digital operation on such digital signal, on the basis of a compensation signal, to generate a compensated signal.

Abstract: The present disclosure refers to a digital microphone device providing a single-bit Pulse Density Modulation PDM output signal. The digital microphone comprises a microphone, arranged to convert an acoustic input signal into an analog electrical signal, and a preamplifier, having a variable gain, arranged to receive the analog electrical signal and to provide an amplified analog electrical signal, depending on the variable gain. The variable gain depends on a gain control signal. The digital microphone further comprises an Analog-to-Digital Converter block, arranged to receive the amplified analog electrical signal and to convert it into a respective digital signal; and a compensation block, arranged to receive the digital signal and to perform a digital operation on such digital signal, on the basis of a compensation signal, to generate a compensated signal.

Abstract: An arithmetic-logic unit for a digital signal processor, processing audio signals, having a multiplier circuit able to receive in input a first and a second signal and to supply in output a third signal which represents the result of the multiplication of said first and second signal, a generator circuit of a dither signal, a summation circuit downline of the multiplier circuit, said summation circuit being able to perform an addition operation between said third signal and the dither signal so as to supply a fourth signal in output, and a truncation or rounding circuit downline of the summation circuit, able to truncate or round said fourth signal.

Abstract: A digital decimation filter includes a set of cascaded integrator stages for generating a first signal comprised of bit words including a first number of bits as well as a set of cascaded derivative stages for receiving said first signal and generating therefrom an output comprised of bit words including a second number of bits. The second number of bits is smaller than said first number of bits and a bit discarding unit is located downstream of the integrator stages and upstream of the derivative stages for discarding a given number of least significant bits from the bit words of the first signal before this is received by the derivative stages. Said given number is defined as the difference between said first and said second number of bits.

Abstract: A set of sampling capacitors weighted according to a binary code is charged through a first capacitive unit, whose capacitance is equal to the sum of the capacitances of the set, at a voltage Vcm−Vin/2. The conversion is carried out by an SAR process by a comparator and a logic unit which operates the switches associated with the capacitors. The final position of the switches is loaded into a register which supplies the digital output signal. To prevent any disturbances in the power supply and reference potential sources from affecting the accuracy of the conversion, two further capacitive units are provided, with the same capacitance as the first capacitive unit. These make it possible to prevent all the disturbances at the input of the comparator in common mode and therefore without any effect on the output.