Abstract: A method of recovering a voltage drop at an output terminal of a voltage compensation circuit connected to a load including a variable load current according to a condition of the load. A circuit portion for a regulator having an output terminal connected to a load including a variable load current may be provided. The circuit portion may include a plurality of stages connected in parallel to said output terminal. Each of said stages may be configured as a current driver having an output connected to the output terminal of said regulator. The circuit portion may include a comparator in each of said stages configured for receiving from a first input a reference voltage value and a predetermined threshold voltage from an other input. Each of said stages may receive a corresponding different threshold voltage value on said other input. The threshold voltage values may be correlated to the variable load current.

Abstract: Provided herein may be a method for controlling program verify operations of a non-volatile memory and a corresponding circuit thereof. The method for controlling a program verify operation of a non-volatile memory, comprising: selecting a source line among source lines coupled to a plurality of planes respectively; measuring a voltage of the selected source line associated with target cells of the non-volatile memory to be verified in a first sensing operation; comparing the measured voltage of the selected source line with a reference voltage; and skipping the second sensing operation if the measured voltage of the selected source line is lower than the reference voltage.

Abstract: Provided herein may be a method for controlling program verify operations of a non-volatile memory and a corresponding circuit thereof. The method for controlling a program verify operation of a non-volatile memory, comprising: selecting a source line among source lines coupled to a plurality of planes respectively; measuring a voltage of the selected source line associated with target cells of the non-volatile memory to be verified in a first sensing operation; comparing the measured voltage of the selected source line with a reference voltage; and skipping the second sensing operation if the measured voltage of the selected source line is lower than the reference voltage.

Abstract: An example of a method reads a spin torque transfer (STT) memory cell, and writes the STT memory cell using information obtained during the reading of the STT memory cell to set a pulse to write the STT memory cell. An example of an apparatus includes a STT memory cell and read/write circuitry coupled to the STT memory cell to determine a read current (IREAD) through the STT memory cell and to set a pulse to write the STT memory cell using IREAD. Additional embodiments are disclosed.

Abstract: An example of a method reads a spin torque transfer (STT) memory cell, and writes the STT memory cell using information obtained during the reading of the STT memory cell to set a pulse to write the STT memory cell. An example of an apparatus includes a STT memory cell and read/write circuitry coupled to the STT memory cell to determine a read current (IREAD) through the STT memory cell and to set a pulse to write the STT memory cell using IREAD. Additional embodiments are disclosed.

Abstract: A controlling block for a non-volatile memory device including a switching element coupling a bit-line with the corresponding page buffer, includes: a look-up table configured to store a plurality of address zones; and a matching logic configured to match one address zone among the plurality of address zones based on an inputted row address and generate a bias voltage, based on the address zone, to the switching element for reading operation of the non-volatile memory, wherein the plurality of address zones are defined by grouping word-lines having a I-V characteristic which differs for a current value different from a prefixed value.

Abstract: An example of a method reads a spin torque transfer (STT) memory cell, and writes the STT memory cell using information obtained during the reading of the STT memory cell to set a pulse to write the STT memory cell. An example of an apparatus includes a STT memory cell and read/write circuitry coupled to the STT memory cell to determine a read current (IREAD) through the STT memory cell and to set a pulse to write the STT memory cell using IREAD. Additional embodiments are disclosed.

Abstract: An example of a method reads a spin torque transfer (STT) memory cell, and writes the STT memory cell using information obtained during the reading of the STT memory cell to set a pulse to write the STT memory cell. An example of an apparatus includes a STT memory cell and read/write circuitry coupled to the STT memory cell to determine a read current (IREAD) through the STT memory cell and to set a pulse to write the STT memory cell using IREAD. Additional embodiments are disclosed.

Abstract: Disclosed herein is a controlling block for a non-volatile memory device including a switching element coupling a bit-line with the corresponding page buffer, comprising: a look-up table configured to store a plurality of address zones: and a matching logic configured to match one address zone among the plurality of address zones based on all inputted row address and generate a bias voltage, based on the address zone, to the switching element for reading operation of the non-volatile memory, wherein the plurality of address zones are defined by grouping word-lines having a I-V characteristic which differs for a current value different from a prefixed value.

Abstract: A non-volatile memory includes a current sensing checking block including a programming status input block comprising a plurality of sub-blocks connected with each other in parallel with respect to a first node; a reference block comprising a plurality of sub-blocks connected with each other in parallel with respect to a second node; an operational amplifier operable to compare voltage levels of the first node and the second node to determine whether a actual number of programming failures for a desired group of cells exceeds a reference number of allowable programming failures of the reference block.

Abstract: An example of a method reads a spin torque transfer (STT) memory cell, and writes the STT memory cell using information obtained during the reading of the STT memory cell to set a pulse to write the STT memory cell. An example of an apparatus includes a STT memory cell and read/write circuitry coupled to the STT memory cell to determine a read current (IREAD) through the STT memory cell and to set a pulse to write the STT memory cell using IREAD. Additional embodiments are disclosed.

Abstract: A method of recovering a voltage drop at an output terminal of a voltage compensation circuit connected to a load including a variable load current according to a condition of the load. A circuit portion for a regulator having an output terminal connected to a load including a variable load current may be provided, The circuit portion may include a plurality of stages connected in parallel to said output terminal. Each of said stages may be configured as a current driver having an output connected to the output terminal of said regulator. The circuit portion may include a comparator in each of said stages configured for receiving from a first input a reference voltage value and a predetermined threshold voltage from an other input. Each of said stages may receive a corresponding different threshold voltage value on said other input. The threshold voltage values may be correlated to the variable load current.

Abstract: A non-volatile memory includes a current sensing checking block including a programming status input block comprising a plurality of sub-blocks connected with each other in parallel with respect to a first node; a reference block comprising a plurality of sub-blocks connected with each other in parallel with respect to a second node; an operational amplifier operable to compare voltage levels of the first node and the second node to determine whether a actual number of programming failures for a desired group of cells exceeds a reference number of allowable programming failures of the reference block.

Abstract: An example of a method reads a spin torque transfer (STT) memory cell, and writes the STT memory cell using information obtained during the reading of the STT memory cell to set a pulse to write the STT memory cell. An example of an apparatus includes a STT memory cell and read/write circuitry coupled to the STT memory cell to determine a read current (IREAD) through the STT memory cell and to set a pulse to write the STT memory cell using IREAD. Additional embodiments are disclosed.

Abstract: An example of a method reads a spin torque transfer (STT) memory cell, and writes the STT memory cell using information obtained during the reading of the STT memory cell to set a pulse to write the STT memory cell. An example of an apparatus includes a STT memory cell and read/write circuitry coupled to the STT memory cell to determine a read current (IREAD) through the STT memory cell and to set a pulse to write the STT memory cell using IREAD. Additional embodiments are disclosed.

Abstract: An example of a method reads a spin torque transfer (STT) memory cell, and writes the STT memory cell using information obtained during the reading of the STT memory cell to set a pulse to write the STT memory cell. An example of an apparatus includes a STT memory cell and read/write circuitry coupled to the STT memory cell to determine a read current (IREAD) through the STT memory cell and to set a pulse to write the STT memory cell using IREAD. Additional embodiments are disclosed.