Patents by Inventor Alessandro Vaccaro
Alessandro Vaccaro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11056383Abstract: Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.Type: GrantFiled: January 26, 2018Date of Patent: July 6, 2021Assignee: Micron Technology, Inc.Inventors: Roberto Somaschini, Alessandro Vaccaro, Paolo Tessariol, Giulio Albini
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Publication number: 20180151415Abstract: Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.Type: ApplicationFiled: January 26, 2018Publication date: May 31, 2018Applicant: Micron Technology, Inc.Inventors: Roberto Somaschini, Alessandro Vaccaro, Paolo Tessariol, Giulio Albini
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Patent number: 9899254Abstract: Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.Type: GrantFiled: March 28, 2017Date of Patent: February 20, 2018Assignee: Micron Technology, Inc.Inventors: Roberto Somaschini, Alessandro Vaccaro, Paolo Tessariol, Giulio Albini
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Publication number: 20170200635Abstract: Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.Type: ApplicationFiled: March 28, 2017Publication date: July 13, 2017Applicant: Micron Technology, Inc.Inventors: Roberto Somaschini, Alessandro Vaccaro, Paolo Tessariol, Giulio Albini
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Patent number: 9627251Abstract: Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.Type: GrantFiled: May 27, 2015Date of Patent: April 18, 2017Assignee: Micron Technology, Inc.Inventors: Roberto Somaschini, Alessandro Vaccaro, Paolo Tessariol, Giulio Albini
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Publication number: 20150262867Abstract: Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.Type: ApplicationFiled: May 27, 2015Publication date: September 17, 2015Inventors: Roberto Somaschini, Alessandro Vaccaro, Paolo Tessariol, Giulio Albini
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Patent number: 9059261Abstract: Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.Type: GrantFiled: June 11, 2014Date of Patent: June 16, 2015Assignee: Micron Technology, Inc.Inventors: Roberto Somaschini, Alessandro Vaccaro, Paolo Tessariol, Giulio Albini
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Publication number: 20140284812Abstract: Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.Type: ApplicationFiled: June 11, 2014Publication date: September 25, 2014Inventors: Roberto Somaschini, Alessandro Vaccaro, Paolo Tessariol, Giulio Albini
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Patent number: 8759980Abstract: Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.Type: GrantFiled: October 29, 2013Date of Patent: June 24, 2014Assignee: Micron Technology, Inc.Inventors: Roberto Somaschini, Alessandro Vaccaro, Paolo Tessariol, Giulio Albini
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Publication number: 20140048956Abstract: Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.Type: ApplicationFiled: October 29, 2013Publication date: February 20, 2014Applicant: Micron Technology, Inc.Inventors: Roberto Somaschini, Alessandro Vaccaro, Paolo Tessariol, Giulio Albini
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Patent number: 8569891Abstract: Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.Type: GrantFiled: March 16, 2010Date of Patent: October 29, 2013Assignee: Micron Technology, Inc.Inventors: Roberto Somaschini, Alessandro Vaccaro, Paolo Tessariol, Giulio Albini