Abstract: An embodiment of a process is described for manufacturing a non volatile memory electronic device integrated on a semiconductor substrate which comprises a matrix of non volatile memory cells, the memory cells being organized in rows, called word lines, and columns, called bit lines and an associated circuitry comprising high voltage transistors and low voltage transistors, the process comprising the steps for realizing: gate electrodes of the non volatile memory cells which comprise at least one first conductive layer, one first insulating layer, one second conductive layer and one third conductive layer and are insulated from the semiconductor substrate by means of a second insulating layer, gate electrodes of high voltage transistors which comprise the at least one first conductive layer whereon the third polysilicon layer is overlapped and is insulated from the semiconductor substrate by means of a third insulating layer of greater thickness than the second insulating layer, gate electrodes of low volt

Abstract: A method manufactures a non-volatile memory device on a semiconductor substrate that includes a matrix of memory cells and associated circuitry. The method includes: forming a filling dielectric layer on the whole substrate until gates of the cells and a conductive layer of the circuitry are completely covered, removing the dielectric layer until upper portions of the gates of the cells and the conductive layer are exposed, defining a plurality of gate electrodes of the transistors of the circuitry in the conductive layer, and forming source and drain regions of the transistors of the circuitry in the substrate. The method also comprises: forming spacers on side walls of gate electrodes of the transistors of the circuitry, and forming a silicide layer on the electrodes of the cells, on the gate electrodes of the transistors of the circuitry and on the source and drain regions of the transistors of said circuitry.

Abstract: A process for manufacturing a non-volatile memory cell including a floating gate MOS transistor, including the steps of: forming a gate dielectric over a surface of a semiconductor material layer; forming a conductive floating gate electrode insulated from the semiconductor material layer by the gate dielectric; forming at least one isolation region laterally to the floating gate electrode; excavating the at least one isolation region; filling the excavated isolation region with a conductive material; and forming a conductive control gate electrode of the floating gate MOS transistor insulatively over the floating gate, wherein the step of forming the floating gate electrode includes: laterally aligning the floating gate electrode to the at least one isolation region; and the step of excavating includes: lowering an isolation region exposed surface below a floating gate electrode exposed surface, the lowering exposing walls of the floating gate electrode; forming a protective layer on exposed walls of the flo

Abstract: A method is described for manufacturing non-volatile memory cells on a semiconductive substrate having active areas bounded by portions of an insulating layer. A thin layer of tunnel oxide is formed and a first layer of conductive material is then deposited. A plurality of floating gate regions are defined by forming stripes of shielding material only above pairs of alternated active areas. Spacers of a selective material are defined with respect to the shielding material and of small width at will in the shelter of the side walls of the stripes thus defined. A shielding material is also deposited on the active areas which lacked it. The formation of the floating gate is completed by leaving the definition of the distance between the floating gate regions to the spacers.

Abstract: A semiconductor substrate has active areas bounded by portions of an insulating layer. A thin layer of tunnel oxide is formed on the substrate and a first layer of conductive material is then deposited. Non-volatile memory cells are manufactured thereon by defining floating gate regions. The definition of these floating gate regions involves defining the first layer of conductive material in order to form a plurality of alternated stripes above pairs of active areas alternated by active areas lacking stripes. Spacers are then formed in the shelter of the side walls of the alternated stripes. A second layer of conductive material is then deposited together with the first layer of conductive material. The spacers are then selectively removed.

Abstract: A method manufactures a non-volatile memory device on a semiconductor substrate that includes a matrix of memory cells and associated circuitry. The method includes: forming a filling dielectric layer on the whole substrate until gates of the cells and a conductive layer of the circuitry are completely covered, removing the dielectric layer until upper portions of the gates of the cells and the conductive layer are exposed, defining a plurality of gate electrodes of the transistors of the circuitry in the conductive layer, and forming source and drain regions of the transistors of the circuitry in the substrate. The method also comprises: forming spacers on side walls of gate electrodes of the transistors of the circuitry, and forming a silicide layer on the electrodes of the cells, on the gate electrodes of the transistors of the circuitry and on the source and drain regions of the transistors of said circuitry.

Abstract: A method is described for manufacturing non-volatile memory cells on a semiconductive substrate having active areas bounded by portions of an insulating layer. A thin layer of tunnel oxide is formed and a first layer of conductive material is then deposited. A plurality of floating gate regions are defined by forming stripes of shielding material only above pairs of alternated active areas. Spacers of a selective material are defined with respect to the shielding material and of small width at will in the shelter of the side walls of the stripes thus defined. A shielding material is also deposited on the active areas which lacked it. The formation of the floating gate is completed by leaving the definition of the distance between the floating gate regions to the spacers.

Abstract: A semiconductor substrate has active areas bounded by portions of an insulating layer. A thin layer of tunnel oxide is formed on the substrate and a first layer of conductive material is then deposited. Non-volatile memory cells are manufactured thereon by defining floating gate regions. The definition of these floating gate regions involves defining the first layer of conductive material in order to form a plurality of alternated stripes above pairs of active areas alternated by active areas lacking stripes. Spacers are then formed in the shelter of the side walls of the alternated stripes. A second layer of conductive material is then deposited together with the first layer of conductive material. The spacers are then selectively removed.

Abstract: A method for forming structures self-aligned with each other on a semiconductor substrate, comprising the following steps: Forming, on the semiconductor substrate, first regions of a first material projecting from the semiconductor substrate; forming, over the whole of the semiconductor substrate, a protective layer of a second material selective with respect to the first material; removing the protective layer to expose said first regions through a planarizing step; etching said first regions to expose said semiconductor substrate, and forming second regions projecting from the substrate of said protective layer. Advantageously, spacers are formed on the sidewalls of the first regions.

Abstract: A non-volatile memory cell is described, being integrated on a semiconductor substrate and comprising: A floating gate transistor including a source region and a drain region, a gate region projecting from the substrate and comprised between the source and drain regions, the gate region having a predetermined length and width and comprising a first floating gate region and a control gate region, in which the floating gate region is insulated laterally, along the width direction, by a dielectric layer with low dielectric constant value. A process for manufacturing non-volatile memory cells on a semiconductor substrate is also described, comprising the following steps: form active areas in the semiconductor substrate bounded by an insulating layer, deposit a first conductor material layer on active areas, define through a standard photolithographic technique a plurality of floating gate regions, form a dielectric layer with low dielectric constant value on the floating gate regions.