Patents by Inventor Alex Bazarsky
Alex Bazarsky has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11709621Abstract: A system and method for read threshold calibration in a non-volatile memory are provided. Physical dies in the memory are divided into groups based on device-level parameters such as time and temperature parameters. An outlier die may be identified outside of the plurality of groups based on a comparison of a bit error rate (BER) indicator for each die to a threshold. For each group of dies, a read parameter is determined for at least one die, and applied to each of the plurality of dies of the group. The read parameter may be determined based on a threshold measurement of a representative one or more word lines.Type: GrantFiled: April 14, 2021Date of Patent: July 25, 2023Assignee: Western Digital Technologies Inc.Inventors: Dudy Avraham, Alex Bazarsky, Evgeny Mekhanik
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Patent number: 11601141Abstract: Apparatuses, systems, and methods are presented for error correction based on physical characteristics for memory. A controller may be configured to read a set of encoded bits from a set of cells of a memory array. The controller may be configured to divide the encoded bits into reliability groups based on one or more persistent physical characteristics associated with cells of the set of cells. The controller may be configured to provide reliability estimates based on the reliability groups to a soft decision decoder for decoding the encoded bits.Type: GrantFiled: February 26, 2021Date of Patent: March 7, 2023Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Gadi Vishne, David Rozman, Alex Bazarsky
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Publication number: 20220278697Abstract: Apparatuses, systems, and methods are presented for error correction based on physical characteristics for memory. A controller may be configured to read a set of encoded bits from a set of cells of a memory array. The controller may be configured to divide the encoded bits into reliability groups based on one or more persistent physical characteristics associated with cells of the set of cells. The controller may be configured to provide reliability estimates based on the reliability groups to a soft decision decoder for decoding the encoded bits.Type: ApplicationFiled: February 26, 2021Publication date: September 1, 2022Applicant: Western Digital Technologies, Inc.Inventors: GADI VISHNE, DAVID ROZMAN, ALEX BAZARSKY
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Patent number: 11321167Abstract: A non-volatile storage system includes a memory controller connected to an integrated memory assembly. The integrated memory assembly includes a memory die comprising non-volatile memory cells and a control die bonded to the memory die. The memory controller provides data to the control die for storage on the memory die. Data is initially stored on the memory die as single bit per memory cell data to increase the performance of the programming process. Subsequently, the control die performs an adaptive folding process which comprises reading the single bit per memory cell data from the memory die, adaptively performing one of multiple decoding options, and programming the data back to the memory die as multiple bit per memory cell data.Type: GrantFiled: May 9, 2020Date of Patent: May 3, 2022Assignee: Western Digital Technologies, Inc.Inventors: Eran Sharon, Alex Bazarsky, Idan Alrod
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Publication number: 20220113894Abstract: A system and method for read threshold calibration in a non-volatile memory are provided. Physical dies in the memory are divided into groups based on device-level parameters such as time and temperature parameters. An outlier die may be identified outside of the plurality of groups based on a comparison of a bit error rate (BER) indicator for each die to a threshold. For each group of dies, a read parameter is determined for at least one die, and applied to each of the plurality of dies of the group. The read parameter may be determined based on a threshold measurement of a representative one or more word lines.Type: ApplicationFiled: April 14, 2021Publication date: April 14, 2022Applicant: Western Digital Technologies Inc.Inventors: Dudy Avraham, Alex Bazarsky, Evgeny Mekhanik
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Patent number: 11244732Abstract: A method for calibrating read threshold voltages includes receiving, from at least one memory die, a number of page bits corresponding to a number of read operations performed on a page associated with the at least one memory die. The method further includes determining voltage bins for each bit of the number of page bits. The method further includes determining, for each voltage bin, a bit error rate. The method further includes adjusting read threshold voltages associated with the at least one memory die using the bite error rate for each voltage bin.Type: GrantFiled: March 26, 2019Date of Patent: February 8, 2022Assignee: Western Digital Technologies, Inc.Inventors: Eran Sharon, Alex Bazarsky, Idan Alrod
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Patent number: 11210183Abstract: Example systems and methods provide differentiated data recovery configurations based on memory health data. A distributed storage system, such as a cloud-based storage system, stores backup data from a remote storage device using a first data recovery configuration. Based on memory health data collected from the remote storage device, a change in a memory health state of the remote storage device may be determined. Responsive to the change in the memory health state, a different data recovery configuration may be used for storing backup data going forward and reallocating previously stored backup data in the distributed storage system.Type: GrantFiled: January 14, 2020Date of Patent: December 28, 2021Assignee: Western Digital Technologies, Inc.Inventors: Ariel Navon, Alex Bazarsky, Eran Sharon, Idan Alrod
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Patent number: 11209998Abstract: Embodiments of the present disclosure generally relate to storage devices, such as SSDs. A data storage device comprises an encrypted interface, one or more flash memory devices, and a controller configured to receive one or more workloads of data through the encrypted interface. Upon a threshold being met, the controller performs a diagnosis of one or more operating parameters of the one or more workloads of data. Based on the diagnosis, the data storage device is optimized by recalibrating one or more of: a partitioning of bits per cell of the one or more flash memory devices, one or more flash management parameters of the data storage device, and a programming rate of the storage device.Type: GrantFiled: September 21, 2018Date of Patent: December 28, 2021Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Yuval Bahar, Avichay Haim Hodes, Alex Bazarsky
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Publication number: 20210349778Abstract: A non-volatile storage system includes a memory controller connected to an integrated memory assembly. The integrated memory assembly includes a memory die comprising non-volatile memory cells and a control die bonded to the memory die. The memory controller provides data to the control die for storage on the memory die. Data is initially stored on the memory die as single bit per memory cell data to increase the performance of the programming process. Subsequently, the control die performs an adaptive folding process which comprises reading the single bit per memory cell data from the memory die, adaptively performing one of multiple decoding options, and programming the data back to the memory die as multiple bit per memory cell data.Type: ApplicationFiled: May 9, 2020Publication date: November 11, 2021Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Eran Sharon, Alex Bazarsky, Idan Alrod
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Publication number: 20210216412Abstract: Example systems and methods provide differentiated data recovery configurations based on memory health data. A distributed storage system, such as a cloud-based storage system, stores backup data from a remote storage device using a first data recovery configuration. Based on memory health data collected from the remote storage device, a change in a memory health state of the remote storage device may be determined. Responsive to the change in the memory health state, a different data recovery configuration may be used for storing backup data going forward and reallocating previously stored backup data in the distributed storage system.Type: ApplicationFiled: January 14, 2020Publication date: July 15, 2021Inventors: Ariel Navon, Alex Bazarsky, Eran Sharon, Idan Alrod
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Publication number: 20210191651Abstract: Apparatuses, systems, and methods are presented for reading data. A controller may be configured to select a read mode from a plurality of read modes for reading data from a region of a non-volatile memory array. The plurality of read modes may include at least a time-based soft bit read mode. The controller may be configured to apply a set of bias conditions to cells of a region so that bit line currents associated with the cells of the region affect voltages at capacitors associated with the cells of the region. The controller may be configured to, in response to selecting a time-based soft bit read mode, read hard bits and soft bits for a region by sensing capacitor voltages resulting from an applied set of bias conditions, at multiple integration times.Type: ApplicationFiled: December 20, 2019Publication date: June 24, 2021Applicant: Western Digital Technologies, Inc.Inventors: ERAN SHARON, ALEX BAZARSKY, IDAN ALROD
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Patent number: 11029889Abstract: Apparatuses, systems, and methods are presented for reading data. A controller may be configured to select a read mode from a plurality of read modes for reading data from a region of a non-volatile memory array. The plurality of read modes may include at least a time-based soft bit read mode. The controller may be configured to apply a set of bias conditions to cells of a region so that bit line currents associated with the cells of the region affect voltages at capacitors associated with the cells of the region. The controller may be configured to, in response to selecting a time-based soft bit read mode, read hard bits and soft bits for a region by sensing capacitor voltages resulting from an applied set of bias conditions, at multiple integration times.Type: GrantFiled: December 20, 2019Date of Patent: June 8, 2021Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Eran Sharon, Alex Bazarsky, Idan Alrod
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Patent number: 11029872Abstract: A non-volatile storage apparatus comprises a non-volatile storage and a control circuit connected to the non-volatile storage. The non-volatile storage structure is organized into multiple partitions. Each partition is preassigned to a different data shaping level. Data to be stored in the non-volatile storage is shaped based on its entropy. The control circuit is configured to write shaped data to a partition of the multiple partitions that is preassigned to a same shaping level as the shaped data.Type: GrantFiled: June 25, 2019Date of Patent: June 8, 2021Assignee: Western Digital Technologies, Inc.Inventors: Ariel Navon, Eran Sharon, Idan Alrod, Alex Bazarsky
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Patent number: 10997080Abstract: In a method for address table cache management, a first logical address associated with a first read command may be received. The first logical address may be associated with a first segment of an address mapping table. A second logical address associated with a second read command may then be received. The second logical address may be associated with a second segment of the address mapping table. A correlation metric associating the first segment to the second segment may be increased in response to receiving the first logical address before the second logical address. The first logical address and second logical address may each map to a physical address within the address mapping table, and a mapping table cache may be configured to store two or more segments. The mapping table cache may then be managed based on the correlation metric.Type: GrantFiled: February 11, 2020Date of Patent: May 4, 2021Assignee: Western Digital Technologies, Inc.Inventors: Tomer Tzvi Eliash, Alex Bazarsky, Ariel Navon, Eran Sharon
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Patent number: 10998041Abstract: In a read scan operation, a first read level window is scanned for a first candidate read level that activates the fewest number of memory cells in relation to other candidate read levels within that window. A second read level window for a second candidate read level is then configured based on a correlation between at least one of the two adjacent memory states and one or more other adjacent memory states associated with the second read level window. The second read level window is scanned for a second candidate read level that activates the fewest number of memory cells, or results in the fewest bit errors, in relation to other candidate read levels within the second read level window. Next, a read operation is configured to use the first candidate read level and the second candidate read level.Type: GrantFiled: May 7, 2020Date of Patent: May 4, 2021Assignee: Western Digital Technologies, Inc.Inventors: Dudy Avraham, Alex Bazarsky, Rotem Feinblat, David Rozman
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Patent number: 10990294Abstract: Technology is disclosed for reading non-volatile memory when a host does not need perfect data. By allowing the memory to return data with some errors, the data will be provided to the host much quicker. Therefore, in response to one or more host read commands, the memory system returns multiple copies of the data over time, progressively getting better so that later in time copies of the data have lower number of errors. The host decides when the error rate is good enough and stops the process (or ignores the rest of the results).Type: GrantFiled: March 26, 2018Date of Patent: April 27, 2021Assignee: Western Digital Technologies, Inc.Inventors: Judah Gamliel Hahn, Alon Marcu, Ariel Navon, Alex Bazarsky, Shay Benisty
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Patent number: 10916306Abstract: A controller for a phase change memory forms a dedicated burst write partition in the phase change memory and initializes memory cells of the dedicated burst write partition to a SET state. Programming of selected memory cells in the dedicated burst write partition is carried out using only RESET pulses.Type: GrantFiled: March 7, 2019Date of Patent: February 9, 2021Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Alex Bazarsky, Idan Alrod, Eran Sharon, Ariel Navon, Chris Petti
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Patent number: 10896131Abstract: Systems and methods for predicting the next host source of a command directed to a storage device, and configuring the storage device with the host memory configuration parameters of that predicted host, are disclosed. A predictive model may be used to identify which of a plurality of different actual or virtual hosts will be sending a next command based on a pattern of prior host origins of commands. The storage device may include a plurality of different memory configuration parameters associated with each different host source and may update the current memory configuration based on the predicted next host origin prior to actual receipt of a next command.Type: GrantFiled: January 28, 2019Date of Patent: January 19, 2021Assignee: Western Digital Technologies, Inc.Inventors: Alex Bazarsky, Ariel Navon, Shay Benisty
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Patent number: 10891052Abstract: A system and method for optimization of non-volatile storage operational parameters is provided. The method may utilize a crowdsourcing server to gather performance data for multiple storage devices connected to respective remotely located host systems. The performance data may be transmitted at regular intervals or at predefined events and the crowdsourcing server may aggregate and determine improved operating parameters for each different type of storage device based on the data gathered for multiple instances of that type of storage device. The optimized operating parameters may be selected from pre-stored and pre-qualified operating parameter sets on the respective storage devices that the crowdsourcing server is aware of. The system includes a non-volatile memory and a controller that is configured to log performance data and transmit at least a portion of that logged data to the crowdsourcing server.Type: GrantFiled: June 26, 2017Date of Patent: January 12, 2021Assignee: Western Digital Technologies, Inc.Inventors: Ariel Navon, Alex Bazarsky, Judah Gamliel Hahn, Eran Sharon
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Patent number: 10866740Abstract: Systems and methods for managing performance and quality of service (QoS) with multiple namespace resource allocation. NVM Express (NVMe) implements a paired submission queue and completion queue mechanism, with host software on the host device placing commands into the submission queue. The memory device processes the commands through various phases including fetching, processing, posting a completion message, and sending an interrupt to the host. NVMe may support the use of namespaces. Namespace configuration may be modified to include performance criteria specific to each namespace. The memory device may then receive commands directed to specific namespaces an apply memory device resources to commands in each namespace queue such that QoS may be applied to control execution of commands such that commands in each namespace receive resources based on host selected performance parameters for each namespace.Type: GrantFiled: October 1, 2018Date of Patent: December 15, 2020Assignee: Western Digital Technologies, Inc.Inventors: Shay Benisty, Ariel Navon, Alex Bazarsky