Abstract: The present disclosure relates to dual beam device and three-dimensional circuit pattern inspection techniques by cross sectioning of inspection volumes with large depth extension exceeding 1 ?m below the surface of a semiconductor wafer, as well as methods, computer program products and apparatuses for generating 3D volume image data of a deep inspection volume inside a wafer without removal of a sample from the wafer. The disclosure further relates to 3D volume image generation and cross section image alignment methods utilizing a dual beam device for three-dimensional circuit pattern inspection.

Abstract: The present disclosure relates to dual beam device and three-dimensional circuit pattern inspection techniques by cross sectioning of inspection volumes with large depth extension exceeding 1 ?m below the surface of a semiconductor wafer, as well as methods, computer program products and apparatuses for generating 3D volume image data of a deep inspection volume inside a wafer without removal of a sample from the wafer. The disclosure further relates to 3D volume image generation and cross section image alignment methods utilizing a dual beam device for three-dimensional circuit pattern inspection.

Abstract: A method of determining a size of a contact area between a first 3D structure and a second 3D structure in an integrated semiconductor sample, includes: obtaining a first cross section image and a second cross section image parallel to the first cross section image, wherein obtaining the first and second cross section images includes subsequently removing a cross section surface layer of the integrated semiconductor sample using a focused ion beam to make a new cross section accessible for imaging, and imaging the new cross section of the integrated semiconductor sample with an imaging device; performing image registration of the obtained cross section images and obtaining a 3D data set; determining a 3D model representing the first 3D structure and the second 3D structure in the 3D data set; and determining a relative overlap of the first 3D structure with the second 3D structure based on the 3D model.

Abstract: A 3D tomographic inspection method for the inspection of semiconductor features in an inspection volume of a semiconductor wafer includes obtaining a 3D tomographic image, and selecting a plurality of 2D cross section images. The method also includes identifying contours of HAR structures, and extracting deviation parameters. The deviation parameters describe fabrication errors such as displacement, deviation in radius or diameter, area or shape.

Abstract: Semiconductor structures can be investigated, e.g., in an in-line quality check. An x-ray scattering measurement, e.g., CD-SAXS, can be used for wafer metrology. The x-ray scattering measurement can be configured based on a slice-and-imaging tomographic measurement using a dual-beam device, e.g., including a focused ion beam device and a scanning electron microscope.

Abstract: A method of determining a size of a contact area between a first 3D structure and a second 3D structure in an integrated semiconductor sample, includes the following steps: obtaining at least a first cross section image and a second cross section image parallel to the first cross section image, wherein obtaining the first and second cross section images includes subsequently removing a cross section surface layer of the integrated semiconductor sample using a focused ion beam to make a new cross section accessible for imaging, and imaging the new cross section of the integrated semiconductor sample with an imaging device; performing image registration of the obtained cross section images and obtaining a 3D data set; determining a 3D model representing the first 3D structure and the second 3D structure in the 3D data set; and determining a relative overlap of the first 3D structure with the second 3D structure based on the 3D model.

Abstract: A method comprises: providing FIB and CPB columns with FIB and CPB optical axes coinciding at a wafer surface; in the coincidence arrangement, removing a cross section surface layer of a measurement site of a wafer using the FIB column to make a new cross section accessible for imaging; reducing a working distance between the CPB imaging column and the wafer surface in a direction along the axis of the CPB imaging column; imaging the new cross section at the measurement site of the wafer with the CPB imaging column at the reduced working distance and thus not in the coincidence arrangement; and increasing the working distance between the CPB imaging column and the wafer surface in the direction along the axis of the CPB imaging column until the coincidence arrangement is reached.

Abstract: A system and a method for volume inspection of semiconductor wafers are configured for milling and fast image acquisition of cross-sections surfaces in an inspection volume. High quality images can be obtained by restriction of the imaging to regions of interest or by averaging over several fast image scans. The method and device can be utilized for quantitative metrology, defect detection, process monitoring, defect review, and inspection of integrated circuits within semiconductor wafers.

Abstract: A system and a method for volume inspection of semiconductor wafers with increased throughput are configured for milling and imaging a reduced number or areas of appropriate cross-sections surfaces in an inspection volume and determining inspection parameters of the 3D objects from the cross-section surface images. The method and device can be utilized for quantitative metrology, defect detection, process monitoring, defect review, and inspection of integrated circuits within semiconductor wafers.

Abstract: A system and a method for volume inspection of semiconductor wafers are configured for milling and imaging of reduced number or areas of appropriate cross-sections surfaces in an inspection volume and determining inspection parameters of the 3D objects from the cross-section surface images. The system and method can be utilized for quantitative metrology, defect detection, process monitoring, defect review, and inspection of integrated circuits within semiconductor wafers.

Abstract: A system and a method for measuring of parameter values of semiconductor objects within wafers with increased throughput include using a modified machine learning algorithm to extract measurement results from instances of semiconductor objects. A training method for training the modified machine learning algorithm includes reducing a user interaction. The method can be more flexible and robust and can involve less user interaction than conventional methods. The system and method can be used for quantitative metrology of integrated circuits within semiconductor wafers.

Abstract: The present invention relates to a method for measuring a sample with a microscope, the method comprising scanning the sample using a focusing plane having a first angle with respect to a top surface of the sample and computing a confidence distance based on the first angle. The method further comprises selecting at least one among a plurality of alignment markers on the sample for performing a lateral alignment of the scanning step and/or for performing a lateral alignment of an output of the scanning step. In particular, the at least one alignment marker selected at the selecting step is chosen among the alignment markers placed within the confidence distance from an intersection of the focusing plane with the top surface.

Abstract: Semiconductor structures can be investigated, e.g., in an in-line quality check. An x-ray scattering measurement, e.g., CD-SAXS, can be used for wafer metrology. The x-ray scattering measurement can be configured based on a slice-and-imaging tomographic measurement using a dual-beam device, e.g., including a focused ion beam device and a scanning electron microscope.

Abstract: The present disclosure provides a method of transferring alignment information from a first set of images to a second set of images, a respective computer program product and a respective inspection device. A first set of cross-section images in a first imaging mode is obtained, the first cross-section images being taken at times Tai. A second set of cross-section images in a second imaging mode is obtained, the second cross-section images being taken at times Tbj, the times Tbj differing from the times Tai. Obtaining the first and second sets of cross-section images comprises subsequently removing a cross-section surface layer of a sample to make a new cross-section accessible for imaging, and imaging the new cross-section of the sample in the first imaging mode or in the second imaging mode. Switching is performed between the first and second imaging modes while obtaining the first and second sets of cross-section images.

Abstract: A system and a method for measuring of parameter values of semiconductor objects within wafers with increased throughput include using a modified machine learning algorithm to extract measurement results from instances of semiconductor objects. A training method for training the modified machine learning algorithm includes reducing a user interaction. The method can be more flexible and robust and can involve less user interaction than conventional methods. The system and method can be used for quantitative metrology of integrated circuits within semiconductor wafers.

Abstract: The present invention relates to a method for measuring a sample with a microscope, the method comprising scanning the sample using a focusing plane having a first angle with respect to a top surface of the sample and computing a confidence distance based on the first angle. The method further comprises selecting at least one among a plurality of alignment markers on the sample for performing a lateral alignment of the scanning step and/or for performing a lateral alignment of an output of the scanning step. In particular, the at least one alignment marker selected at the selecting step is chosen among the alignment markers placed within the confidence distance from an intersection of the focusing plane with the top surface.

Abstract: The present disclosure relates to dual beam device and three-dimensional circuit pattern inspection techniques by cross sectioning of inspection volumes with large depth extension exceeding 1 ?m below the surface of a semiconductor wafer, as well as methods, computer program products and apparatuses for generating 3D volume image data of a deep inspection volume inside a wafer without removal of a sample from the wafer. The disclosure further relates to 3D volume image generation and cross section image alignment methods utilizing a dual beam device for three-dimensional circuit pattern inspection.

Abstract: A method of determining a size of a contact area between a first 3D structure and a second 3D structure in an integrated semiconductor sample, includes the following steps: obtaining at least a first cross section image and a second cross section image parallel to the first cross section image, wherein obtaining the first and second cross section images includes subsequently removing a cross section surface layer of the integrated semiconductor sample using a focused ion beam to make a new cross section accessible for imaging, and imaging the new cross section of the integrated semiconductor sample with an imaging device; performing image registration of the obtained cross section images and obtaining a 3D data set; determining a 3D model representing the first 3D structure and the second 3D structure in the 3D data set; and determining a relative overlap of the first 3D structure with the second 3D structure based on the 3D model.

Abstract: A 3D tomographic inspection method for the inspection of semiconductor features in an inspection volume of a semiconductor wafer includes obtaining a 3D tomographic image, and selecting a plurality of 2D cross section images. The method also includes identifying contours of HAR structures, and extracting deviation parameters. The deviation parameters describe fabrication errors such as displacement, deviation in radius or diameter, area or shape.

Abstract: A three-dimensional circuit pattern inspection technique includes cross sectioning integrated circuits for obtaining a 3D volume image of an integrated semiconductor sample. The method employs a feature based alignment of cross section images based on features of an integrated semiconductor sample. A computer program product and apparatus are provided.