Abstract: A decision directed flicker noise canceller for reducing flicker noise in a modulated input signal according to an embodiment of the present invention includes a decision circuit, a conversion circuit, first and second adders and a filter. The decision circuit provides signal decisions based on the input signal. The conversion circuit provides selected signal values based on the signal decisions. The first adder subtracts the selected signal values from signals based on the input signal to provide a flicker noise estimate. The filter receives and filters the flicker noise estimate and the second adder subtracts the filtered flicker noise estimate from the input signal and provides a corrected input signal. In a feedback configuration, the second adder is located in a feedback position before the decision circuit in the signal processing path. In a feed-forward configuration, the second adder is located in a feed-forward position after the decision circuit.

Abstract: An adaptive frequency equalization system providing an equalizer that has programmable taps that adjusts magnitude and phase of symbol information of a received signal and that provides equalized symbol information. The system includes a hard decision circuit that selects ideal symbol values using the equalized symbol information. A frequency response circuit determines frequency response update values using the ideal symbol values and the received signal. An adjust circuit updates stored frequency response information using the frequency response update values, and also updates the programmable taps of the equalizer using the stored frequency response information.

Abstract: A decision directed flicker noise canceller for reducing flicker noise in a modulated input signal according to an embodiment of the present invention includes a decision circuit, a conversion circuit, first and second adders and a filter. The decision circuit provides signal decisions based on the input signal. The conversion circuit provides selected signal values based on the signal decisions. The first adder subtracts the selected signal values from signals based on the input signal to provide a flicker noise estimate. The filter receives and filters the flicker noise estimate and the second adder subtracts the filtered flicker noise estimate from the input signal and provides a corrected input signal. In a feedback configuration, the second adder is located in a feedback position before the decision circuit in the signal processing path. In a feed-forward configuration, the second adder is located in a feed-forward position after the decision circuit.

Abstract: An adaptive frequency equalization system providing an equalizer that has programmable taps that adjusts magnitude and phase of symbol information of a received signal and that provides equalized symbol information. The system includes a hard decision circuit that selects ideal symbol values using the equalized symbol information. A frequency response circuit determines frequency response update values using the ideal symbol values and the received signal. An adjust circuit updates stored frequency response information using the frequency response update values, and also updates the programmable taps of the equalizer using the stored frequency response information.

Abstract: A decision directed flicker noise canceller for reducing flicker noise in a modulated input signal according to an embodiment of the present invention includes a decision circuit, a conversion circuit, first and second adders and a filter. The decision circuit provides signal decisions based on the input signal. The conversion circuit provides selected signal values based on the signal decisions. The first adder subtracts the selected signal values from signals based on the input signal to provide a flicker noise estimate. The filter receives and filters the flicker noise estimate and the second adder subtracts the filtered flicker noise estimate from the input signal and provides a corrected input signal. In a feedback configuration, the second adder is located in a feedback position before the decision circuit in the signal processing path. In a feed-forward configuration, the second adder is located in a feed-forward position after the decision circuit.

Abstract: An adaptive frequency equalization system providing an equalizer that has programmable taps that adjusts magnitude and phase of symbol information of a received signal and that provides equalized symbol information. The system includes a hard decision circuit that selects ideal symbol values using the equalized symbol information. A frequency response circuit determines frequency response update values using the ideal symbol values and the received signal. An adjust circuit updates stored frequency response information using the frequency response update values, and also updates the programmable taps of the equalizer using the stored frequency response information.

Abstract: A decision directed flicker noise canceller for reducing flicker noise in a modulated input signal according to an embodiment of the present invention includes a decision circuit, a conversion circuit, first and second adders and a filter. The decision circuit provides signal decisions based on the input signal. The conversion circuit provides selected signal values based on the signal decisions. The first adder subtracts the selected signal values from signals based on the input signal to provide a flicker noise estimate. The filter receives and filters the flicker noise estimate and the second adder subtracts the filtered flicker noise estimate from the input signal and provides a corrected input signal. In a feedback configuration, the second adder is located in a feedback position before the decision circuit in the signal processing path. In a feed-forward configuration, the second adder is located in a feed-forward position after the decision circuit.

Abstract: A system and method for controlling amplification of a signal received by a ZIF radio having a power level within a full power range relative to a minimum noise floor. The ZIF radio includes a ZIF receiver front end, an overload detector, an ADC, a saturation detector, a DC and power estimator, and control logic. The control logic utilized full visibility of the ADC to limit gain of the baseband amplifier to a maximum gain setting sufficient to view the minimum noise floor and to view a received signal having a power level within any of several segments of the power spectrum. The segmentation of the power spectrum is based on an overload condition of the ZIF receiver front end and a saturation condition of the ADC. The control logic further employs limited gain stepping of the baseband amplifier to avoid exceeding a DC budget of the ADC.

Abstract: A method and system for determining gain taps values for a pre-compensation transmit frequency domain equalizer of a wireless transmitter. Each tap of the equalizer scales a zone and each zone includes at least one sub-carrier. To reduce the number of taps, one or more zones may incorporate more than one sub-carrier. The method includes providing test information for processing by the transmitter, measuring sub-carrier magnitudes generated by the transmitter, normalizing the measured sub-carrier magnitudes, determining an average power value of the normalized sub-carrier magnitudes within each sub-carrier zone, and finding a gain value for each sub-carrier zone so that when multiplied by the average power value of that sub-carrier zone comes closest to a predetermined target value. The normalizing, determining and finding may be repeated for multiple target values to generate a multiple arrays of gain values, where one array that is closest to achieving a unity power gain is selected.