Patents by Inventor Alex Chew

Alex Chew has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for color calibrating multiple displays and system therefor
    Patent number: 10991284
    Abstract: A system includes a monitor stand configured to mount two or more display devices. The monitor stand includes an extension arm having an integral color calibration device. The extension arm can be manipulated to selectively position the color calibration device in contact with a light-emitting portion of each display device, and can be collapsed for stowage adjacent to the monitor stand. The system further controls the color calibration device to determine initial color attributes of each display device.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: April 27, 2021
    Assignee: Dell Products L.P.
    Inventors: Choon Keat (Alex) Chew, Wei Wei Wilson Chua, Chih-Hao (Gisir) Kao
  • Method for Color Calibrating Multiple Displays and System Therefor
    Publication number: 20210056877
    Abstract: A system includes a monitor stand configured to mount two or more display devices. The monitor stand includes an extension arm having an integral color calibration device. The extension arm can be manipulated to selectively position the color calibration device in contact with a light-emitting portion of each display device, and can be collapsed for stowage adjacent to the monitor stand. The system further controls the color calibration device to determine initial color attributes of each display device.
    Type: Application
    Filed: August 20, 2019
    Publication date: February 25, 2021
    Inventors: Choon Keat (Alex) Chew, Wei Wei Wilson Chua, Chih-Hao (Gisir) Kao
  • Package design and method of manufacture for chip grid array
    Patent number: 7456496
    Abstract: A chip level package utilizing a CGA is described. A semiconductor chip with pillars is molded in an encapsulant. Solder balls are added and connected to the chip pillars. The final package does not require a first level substrate or interposer and is able to be assembled to the next level as is. An additional embodiment describes the addition of a thermal heat sink to the packaged chip.
    Type: Grant
    Filed: May 12, 2005
    Date of Patent: November 25, 2008
    Assignee: Advanpack Solutions Pte Ltd
    Inventors: Tan Kim Hwee, Roman Perez, Kee Kwang Lau, Alex Chew, Antonio Dimaano
  • Test socket for an integrated circuit
    Patent number: 7307443
    Abstract: A test socket for an integrated circuit, wherein the test socket has a first plurality of test points for making electrical contact with contacts of a laminate package and a second plurality of test points for making electrical contact with contacts of a lead frame package. The test socket is suitable for testing, at one time: a laminate package, or a lead frame package, or both a laminate package and a lead frame package.
    Type: Grant
    Filed: November 17, 2006
    Date of Patent: December 11, 2007
    Assignee: Infineon Technologies AG
    Inventors: Chye Lin Toh, Boon Kiat Alex Chew
  • Package design and method of manufacture for chip grid array
    Publication number: 20050205987
    Abstract: A chip level package utilizing a CGA is described. A semiconductor chip with pillars is molded in an encapsulant. Solder balls are added and connected to the chip pillars. The final package does not require a first level substrate or interposer and is able to be assembled to the next level as is. An additional embodiment describes the addition of a thermal heat sink to the packaged chip.
    Type: Application
    Filed: May 12, 2005
    Publication date: September 22, 2005
    Inventors: Tan Hwee, Roman Perez, Kee Lau, Alex Chew, Antonio Dimaano
  • Package design and method of manufacture for chip grid array
    Patent number: 6929981
    Abstract: A chip level package utilizing a CGA is described. A semiconductor chip with pillars is molded in an encapsulant. Solder balls are added and connected to the chip pillars. The final package does not require a first level substrate or interposer and is able to be assembled to the next level as is. An additional embodiment describes the addition of a thermal heat sink to the packaged chip.
    Type: Grant
    Filed: September 6, 2002
    Date of Patent: August 16, 2005
    Assignee: Advanpack Solutions PTE, Ltd.
    Inventors: Tan Kim Hwee, Roman Perez, Kee Kwang Lau, Alex Chew, Antonio Dimaano
  • Flip chip package using no-flow underfill and method of fabrication
    Publication number: 20050087883
    Abstract: A design and method of fabrication for a semiconductor package is described. A solder bumped semiconductor chip is assembled to a metallized package substrate utilizing the solder bumps. The interconnecting solder bumps are properly constrained at assembly by the introduction of a no-flow underfill between the chip and the substrate. The no-flow underfill constrains the solder of the solder bumps so as to maintain the desired size and shape.
    Type: Application
    Filed: October 22, 2003
    Publication date: April 28, 2005
    Inventors: Tan Hwee, Roman Perez, Antonio Dimaano, Lau Kwang, Alex Chew
  • Leadless semiconductor packaging structure with inverted flip chip and methods of manufacture
    Publication number: 20040108580
    Abstract: A semiconductor chip packaging structure is described. The structure comprising of a semiconductor chip interconnected to a recessed lead frame and the resultant assembly encapsulated in a molding compound. The final product is a reverse mounted semiconductor chip in a leadless quad flat pack configuration. A second embodiment allows for the semiconductor chip backside to be exposed for thermal enhancements. Manufacturing methods are also described for the two embodiments disclosed.
    Type: Application
    Filed: December 9, 2002
    Publication date: June 10, 2004
    Applicant: Advanpack Solutions Pte. Ltd.
    Inventors: Kim Hwee Tan, Roman Perez, Kee Kwang Lau, Alex Chew, Antonio Dimaano
  • Semiconductor chip grid array package design and method of manufacture
    Patent number: 6734039
    Abstract: A chip level package utilizing a CGA is described. A semiconductor chip with pillars is molded in an encapsulant. Solder balls are added and connected to the chip pillars. The final package does not require a first level substrate or interposer and is able to be assembled to the next level as is.
    Type: Grant
    Filed: September 6, 2002
    Date of Patent: May 11, 2004
    Assignee: Advanpack Solutions Pte Ltd.
    Inventors: Tan Kim Hwee, Roman Perez, Kee Kwang Lau, Alex Chew, Antonio Dimaano
  • Method for constraining the spread of solder during reflow for preplated high wettability lead frame flip chip assembly
    Publication number: 20040084508
    Abstract: A method and structure for controlling solder spread in a predefined/designed area during flip chip assembly build is disclosed. Using conventional processes used in the art blind holes or dimples are incorporated onto the lead frame which then act as containers or wells trapping the solder and thereby preventing it from spreading wider.
    Type: Application
    Filed: October 30, 2002
    Publication date: May 6, 2004
    Applicant: Advanpack Solutions Pte. Ltd.
    Inventors: John Briar, Roman Perez, Kee Kwang Lau, Alex Chew
  • Semiconductor chip grid array package design and method of manufacture
    Publication number: 20040046238
    Abstract: A chip level package utilizing a CGA is described. A semiconductor chip with pillars is molded in an encapsulant. Solder balls are added and connected to the chip pillars. The final package does not require a first level substrate or interposer and is able to be assembled to the next level as is.
    Type: Application
    Filed: September 6, 2002
    Publication date: March 11, 2004
    Applicant: Advanpack Solutions Pte Ltd.
    Inventors: Tan Kim Hwee, Roman Perez, Kee Kwang Lau, Alex Chew, Antonio Dimaano
  • Package design and method of manufacture for chip grid array
    Publication number: 20040046257
    Abstract: A chip level package utilizing a CGA is described. A semiconductor chip with pillars is molded in an encapsulant. Solder balls are added and connected to the chip pillars. The final package does not require a first level substrate or interposer and is able to be assembled to the next level as is. An additional embodiment describes the addition of a thermal heat sink to the packaged chip.
    Type: Application
    Filed: September 6, 2002
    Publication date: March 11, 2004
    Applicant: Advanpack Solutions Pte.Ltd.
    Inventors: Tan Kim Hwee, Roman Perez, Kee Kwang Lau, Alex Chew, Antonio Dimaano