Abstract: Various embodiments relate to digital demodulation for wireless power transmission. A wireless power transmitter includes a transmitter coil and a controller. The transmitter coil is configured to wirelessly couple to a receiver coil of a wireless power receiver to transfer power to the wireless power receiver responsive to a coil current applied to the transmitter coil. The wireless power receiver is configured to modulate at least one electrical condition of the wireless power receiver to modulate the coil current at the transmitter coil. The controller is configured to sample one or more electrical signals of the wireless power transmitter, and digitally demodulate the sampled one or more electrical signals to obtain a communication received from the wireless receiver responsive to the modulation of the at least one electrical condition of the wireless power receiver.

Abstract: Adaptive slope compensation for current mode control in a switch mode power supply converter is computed for every switching cycle based upon the input voltage and duty-cycle whereby the quality factor is maintained at a constant value. A digital signal processing (DSP) capable microcontroller comprises a voltage loop compensator and generates a desired current reference for every switching cycle. Slope calculations are adapted for switching frequency, inductance value, current circuit gain, etc. The slope calculation result is applied to a pulse-digital-modulation (PDM) digital-to-analog converter (DAC) capable of changing its output levels at a very fast rate compared to the power supply switching frequency whereby the required current slope is provided within the switching period. Actual inductor current may be used to compare against the slope reference, thereby taking care of changes in the inductance values under load. The slope levels are automatically changed when the switching frequency is changed.

Abstract: A circuit arrangement, signal processor, and method for interleaved switched boundary mode power conversion are disclosed. The circuit arrangement comprises at least an input for receiving an alternating input voltage from a power supply; an output to provide an output voltage to a load; a first interleaved circuit comprising: a first energy storage device; and a first controllable switching device; and one or more secondary interleaved circuits, each comprising: a secondary energy storage device; and a secondary controllable switching device; and a signal processor.

Abstract: Adaptive slope compensation for current mode control in a switch mode power supply converter is computed for every switching cycle based upon the input voltage and duty-cycle whereby the quality factor is maintained at a constant value. A digital signal processing (DSP) capable microcontroller comprises a voltage loop compensator and generates a desired current reference for every switching cycle. Slope calculations are adapted for switching frequency, inductance value, current circuit gain, etc. The slope calculation result is applied to a pulse-digital-modulation (PDM) digital-to-analog converter (DAC) capable of changing its output levels at a very fast rate compared to the power supply switching frequency whereby the required current slope is provided within the switching period. Actual inductor current may be used to compare against the slope reference, thereby taking care of changes in the inductance values under load. The slope levels are automatically changed when the switching frequency is changed.

Abstract: A circuit arrangement, a signal processor, and a method of interleaved switched boundary mode power conversion are disclosed. The circuit arrangement comprises at least an input for receiving an input voltage from a power supply; an output to provide an output voltage to a load; a first interleaved circuit comprising a first energy storage device and a first controllable switching device; one or more secondary interleaved circuits, each comprising a secondary energy storage device, and a secondary controllable switching device; and a signal processor, connected to the controllable switching devices. The signal processor comprises a first switching cycle controller, configured for cycled zero-current switching operation of the first controllable switching device; and one or more secondary switching cycle controllers, configured for cycled zero-current switching operation of the secondary controllable switching devices.

Abstract: A circuit arrangement for switched boundary mode power conversion, a corresponding signal processor and a method of switched boundary mode power conversion are provided. The circuit arrangement comprises an input for receiving an input voltage from a power supply, an output to provide an output voltage to a load, an energy storage device, a controllable switching device, and a signal processor. The signal processor is connected to the controllable switching device and being configured for zero-current switching of the switching device, wherein the signal processor is further configured to determine at least one switching point for the zero-current switching from a first voltage signal and a second voltage signal, wherein the first voltage signal corresponds to the input voltage and the second voltage signal corresponds to the output voltage.

Abstract: A circuit arrangement for switched boundary mode power conversion, a corresponding signal processor and a method of switched boundary mode power conversion are provided. The circuit arrangement comprises an input for receiving an input voltage from a power supply, an output to provide an output voltage to a load, an energy storage device, a controllable switching device, and a signal processor. The signal processor is connected to the controllable switching device and being configured for zero-current switching of the switching device. The signal processor is further configured to determine an on-time period for the switching device in one or more switching cycles based on the output voltage and the output of a crossover frequency control module to provide an improved transient response characteristic of the circuit arrangement.

Abstract: A circuit arrangement for switched boundary mode power conversion, a corresponding signal processor and a method of switched boundary mode power conversion are provided. The circuit arrangement comprises an input for receiving an input voltage from a power supply, an output to provide an output voltage to a load, an energy storage device, a controllable switching device, and a signal processor. The signal processor is connected to the controllable switching device and being configured for zero-current switching of the switching device. The signal processor is further configured to determine an on-time period for the switching device in one or more switching cycles based on the output voltage and the output of a crossover frequency control module to provide an improved transient response characteristic of the circuit arrangement.

Abstract: A circuit arrangement, signal processor, and method for interleaved switched boundary mode power conversion are disclosed. The circuit arrangement comprises at least an input for receiving an alternating input voltage from a power supply; an output to provide an output voltage to a load; a first interleaved circuit comprising: a first energy storage device; and a first controllable switching device; and one or more secondary interleaved circuits, each comprising: a secondary energy storage device; and a secondary controllable switching device; and a signal processor.

Abstract: A circuit arrangement for switched boundary mode power conversion, a corresponding signal processor and a method of switched boundary mode power conversion are provided. The circuit arrangement comprises an input for receiving an input voltage from a power supply, an output to provide an output voltage to a load, an energy storage device, a controllable switching device, and a signal processor. The signal processor is connected to the controllable switching device and being configured for zero-current switching of the switching device, wherein the signal processor is further configured to determine at least one switching point for the zero-current switching from a first voltage signal and a second voltage signal, wherein the first voltage signal corresponds to the input voltage and the second voltage signal corresponds to the output voltage.

Abstract: A circuit arrangement, a signal processor, and a method of interleaved switched boundary mode power conversion are disclosed. The circuit arrangement comprises at least an input for receiving an input voltage from a power supply; an output to provide an output voltage to a load; a first interleaved circuit comprising a first energy storage device and a first controllable switching device; one or more secondary interleaved circuits, each comprising a secondary energy storage device, and a secondary controllable switching device; and a signal processor, connected to the controllable switching devices. The signal processor comprises a first switching cycle controller, configured for cycled zero-current switching operation of the first controllable switching device; and one or more secondary switching cycle controllers, configured for cycled zero-current switching operation of the secondary controllable switching devices.

Abstract: In a debugging method for an integrated circuit device which has multiple processing cores, a debugging breakpoint is activated at a first processor core in the integrated circuit device. Upon activation, the debugging breakpoint stops execution of instructions in the first processor core and the debugging breakpoint is communicated to a second processor core in the integrated circuit device.

Abstract: A microcontroller device has a housing with a plurality of external pins having a plurality of input/output pins, a first microcontroller with a first central processing unit (CPU), a first system bus coupled with the first CPU, first memory coupled with the first system bus, and a first plurality of peripheral devices coupled with the first system bus, a second microcontroller with a second central processing unit (CPU), a second system bus coupled with the second CPU, second memory coupled with the second system bus, and a second plurality of peripheral devices coupled with the second system bus, and a pad ownership multiplexer unit being controllable to assign control of the input/output pins to either the first microcontroller or the second microcontroller, wherein the number of external pins is less than the sum of a data buswidth of the first and second microcontroller.

Abstract: A microcontroller device has a housing with a plurality of external pins a first microcontroller with a first central processing unit (CPU), a first system bus coupled with the first CPU, first memory coupled with the first system bus, and a first plurality of peripheral devices coupled with the first system bus, and a second microcontroller with a second central processing unit (CPU), a second system bus coupled with the second CPU, second memory coupled with the second system bus, and a second plurality of peripheral devices coupled with the second system bus, wherein first and second microcontroller communicate only via a dedicated interface.

Abstract: A microcontroller device has a housing with a plurality of external pins a first microcontroller with a first central processing unit (CPU), a first system bus coupled with the first CPU, first memory coupled with the first system bus, and a first plurality of peripheral devices coupled with the first system bus, and a second microcontroller with a second central processing unit (CPU), a second system bus coupled with the second CPU, second memory coupled with the second system bus, and a second plurality of peripheral devices coupled with the second system bus, wherein first and second microcontroller communicate only via a dedicated interface.

Abstract: A number of standard PWM generators produce PWM signals that may be used to drive the power stages for Full-Bridge, Feed-Forward, Push-Pull, Phase-Shift Zero Voltage Transition (ZVT), and other switched mode power supply (SMPS) conversion topologies. These PWM signals may be fed to logic functions of a combinatorial logic block. Appropriate PWM signals are selected as operands along with desired logic function(s) that operates on these input operands. The resultant combinatorial PWM signals may then be used directly or may be fed through dead-time processing circuitry prior to outputting to an application circuit. In addition to the combinatorial logic functions, sequential logic functions may also be used to provide sequential PWM signals, e.g., synchronous sequential, asynchronous sequential, and/or sequential-combinatorial PWM signals.

Abstract: A microcontroller device has a housing with a plurality of external pins having a plurality of input/output pins, a first microcontroller with a first central processing unit (CPU), a first system bus coupled with the first CPU, first memory coupled with the first system bus, and a first plurality of peripheral devices coupled with the first system bus, a second microcontroller with a second central processing unit (CPU), a second system bus coupled with the second CPU, second memory coupled with the second system bus, and a second plurality of peripheral devices coupled with the second system bus, and a pad ownership multiplexer unit being controllable to assign control of the input/output pins to either the first microcontroller or the second microcontroller, wherein the number of external pins is less than the sum of a data buswidth of the first and second microcontroller.

Abstract: A slope compensation module provides slope compensation of a switched-mode power supply using current mode control. This slope compensation function may be provided by a digital slope compensation generator and a pulse density modulated digital-to-analog converter (PDM DAC) having a selectable response mode low pass filter.

Abstract: A plurality of PWM generators have user configurable time delay circuits for each PWM control signal generated therefrom. The time delay circuits are adjusted so that each of the PWM control signals arrive at their associated power transistors at the same time. This may be accomplished by determining a maximum delay time of the PWM control signal that has to traverse the longest propagation time and then setting the delay for that PWM control signal to substantially zero delay. Thereafter, all other delay time settings for the other PWM control signals may be determined by subtracting the propagation time for each of the other PWM control signals from the longest propagation time. Thereby insuring that all of the PWM control signals arrive at their respective power transistor control nodes with substantially the same time relationships as when they left their respective PWM generators.

Abstract: A slope compensation module provides slope compensation of a switched-mode power supply using current mode control. This slope compensation function may be provided by a digital slope compensation generator and a pulse density modulated digital-to-analog converter (PDM DAC) having a selectable response mode low pass filter.