Abstract: A boundary addressable memory (BAM) array comprises a plurality of BAM word modules, each BAM work module comprises a plurality of BAM cells for performing arithmetic comparisons between input data and an upper bound value and a lower bound value stored in each BAM cell to generate a matching signal indicating whether the input data is not greater than the upper bound value and not less than the lower bound value or whether the input data is not greater than the lower bound value and not less than the upper bound value.

Abstract: A low power wired OR circuit of the present invention comprises a plurality of logic blocks for pulling a wired OR signal line low in response to certain conditions, a differential pair of lines, such as the wired OR signal line and a reference signal line, and a sensing device coupled to the reference signal line and the wired OR signal line to receive the wired OR signal and the reference signal respectively and to detect a difference between the two signals. Having a differential pair of lines is advantageous because it maintains noise immunity for small voltage swings on the wired OR signal line, thereby reducing power dissipation in the wired OR circuit. A common current source coupled to each logic block through a common return path allows the low power wired OR circuit to control a discharge rate at which the wired OR line discharges.

Abstract: The invention provides apparati and methods for processing a packet. The processing is done according to a table and context based scheme.

Abstract: In a services processor, a queue operations unit controls the output of processed data packets from the services processor. In accordance with a hybrid list/calendar queue priority scheme, the queue operations unit uses a unique data structure comprising a tree of calendar arrays and queue lists to schedule the data packets for output.

Abstract: A services processor includes an editing unit, which performs various functions for editing data packets, such as packet creation, packet encapsulation, and packet replication.

Abstract: A system for mapping a sparsely populated virtual space of variable sized memory objects to a more densely populated physical address space of fixed size memory elements for use by a host processor comprises an object cache for caching frequently accessed memory elements and an object manager for managing the memory objects used by the host processor. The object manager may further comprise an address translation table for translating virtual space addresses for memory objects received from the host processor to physical space addresses for memory elements, and a management table for storing data associated with the memory objects used by the host processor.

Abstract: A logic circuit comprises a dual rail drive circuit having a first rail and a second rail. The logic circuit further comprises a logic block having a first input coupled to receive an input signal from the first rail of the dual rail driver, and a second input coupled to receive an input signal from the second rail of the dual rail driver. In one embodiment, the input signal from the first rail of the dual rail driver can swing to a voltage level sufficient to turn on a p-channel transistor, and the input signal from the second rail of the dual rail driver can swing to a voltage level sufficient to turn on an n-channel transistor. For example, for a 0.18 micron process the input signal from the first rail may have a voltage swing from VDD to VDD-400 MV, and the input signal from the second rail may a voltage swing from GROUND to 400 MV.

Abstract: A low power wired OR circuit of the present invention comprises a plurality of logic blocks for pulling a wired OR signal line low in response to certain conditions, a differential pair of lines, such as the wired OR signal line and a reference signal line, and a sensing device coupled to the reference signal line and the wired OR signal line to receive the wired OR signal and the reference signal respectively and to detect a difference between the two signals. Having a differential pair of lines is advantageous because it maintains noise immunity for small voltage swings on the wired OR signal line, thereby reducing power dissipation in the wired OR circuit. A common current source coupled to each logic block through a common return path allows the low power wired OR circuit to control a discharge rate at which the wired OR line discharges.

Abstract: A switch-based network processor disclosed. The switch-based network processor includes a packet parser, search and modification scheduler that parses a data packet, develops a search for a processing rule associated with the packet, and schedules a modification to be performed on the packet based on the rule. The processor also includes several search resources that each can search simultaneously for a processing rule. Multiple packet modifiers are included to modify several packets simultaneously. A core switch is also provided to switch search requests from the parser to the search resources, to switch search responses from the search resources to the parser, and to switch modification requests and responses between the parser and packet modifiers. The switch-based processor also includes a session state storage device that can be used to allow the processor to be aware of a session.

Abstract: A system and method for operating an associative memory cache device in a computer system. The system comprises a search client configured to search for data in a caching associative memory such as a content addressable memory (CAM); a caching associative memory element coupled to the search client for generating a matching signal; and a associative memory element coupled to the caching associative element configured to search for data not stored in the caching associative memory element. The search client issues a search request for data to associative cache element. If the matching data is found there, then such matching data is returned to the search client. Alternatively, if the data is not found, then the search request is issued to the main associative memory. The least frequently used data or the least recently used data in the associative memory cache are replaced with the matching data and the higher priority data.

Abstract: A content addressable memory device is provided which may include a novel CAM cell structure which reduces the total power dissipated by the CAM and improves the match time for the CAM. The novel CAM cell structure may include a CMOS implemented compare cell and a wide AND gate which combines the match decisions for each CAM cell into a match decision. The CAM cell structure may be implemented in a variety of different CAM devices, including dual port CAM devices, CAM devices with individual bit masking, event co-processors and database co-processors.

Abstract: A content addressable memory device is provided which may include a novel CAM cell structure which reduces the total power dissipated by the CAM and improves the match time for the CAM. The novel CAM cell structure may include a CMOS implemented compare cell and a wide AND gate which combines the match decisions for each CAM cell into a match decision. The CAM cell structure may be implemented in a variety of different CAM devices, including dual port CAM devices, CAM devices with individual bit masking, event co-processors and database co-processors.

Abstract: A content addressable memory device is provided which may include a novel CAM cell structure which reduces the total power dissipated by the CAM and improves the match time for the CAM. The novel CAM cell stnictuire may include a CMOS implemented compare cell and a wide AND gate which combines the match decisions for each CAM cell into a match decision. The CAM cell structure may be implemented in a variety of different CAM devices, including dual port CAM devices, CAM devices with individual bit masking, event co-processors and database co-processors.

Abstract: An apparatus for selecting a reference line for image data compression including a plurality of mutually connected reference selector chips for selecting a reference scan line from vertical mode coding of image data. The reference selector chips select a reference scan line from a plurality of preceding scan lines in exclusive or combination of the image data of each candidate reference scan line with the image data from the input scan line. The candidate reference scan line that has the lowest number of dissimilar bits is selected as the reference scan line. Each candidate reference scan line has associated therewith a register having bit positions arranged from the highest order bit position to a lowest order bit position for storing a binary sum of the number of dissimilar bits. When the sums are compared, the binary value and successive bit positions are compared from the highest order bit position to the lowest order bit position.

Abstract: A method and apparatus for improving the performance of data compression processes, such as relative address coding, CCITT standard facsimile processes, and similar two-dimensional image coding processes, by block coding one or more of the vertical mode codes produced by these processes. The performance of data compression processes is improved by representing one or more sequences of vertical mode code words with a single block code word. A reference scan line is preferably selected from among a plurality of previous scan lines, for example, the immediately preceding ten scan lines, for two-dimensional image coding. The previous scan line which is most similar to the current scan line to be coded is selected as the reference scan line. The selected reference scan line is then fed with the current scan line to be coded to a two-dimensional data compression coding process so as to yield a first tier of data compression.

Abstract: A method and apparatus for selecting a reference scan line for two-dimensional image coding preferably compatible with known facsimile transmission equipment are disclosed. Selection of a reference scan line in accordance with the method and apparatus of the invention allows data compression for facsimile transmission so that the cost for use of the communication link is reduced. More than one previous scan line is considered as a candidate reference scan line. A reference scan line is selected from among a plurality of previous scan lines, for example, the immediately preceding ten scan lines. The preselected or adaptively selected scan line among the multiple prior scan lines, more particularly, the previous scan line which is most similar to the current scan line to be coded, is selected as the reference scan line. The reference scan line is then fed with the current scan line to be coded to a two-dimensional data compression coding process so as to yield optimum data compression.