Abstract: A processor of an information handling system (IHS) initiates an L3 cache prefetch operation in response to a demand load during instruction processing. The processor selects an L3 cache prefetch at random for tracking as a target prefetched instruction. The processor initiates an L1 cache target prefetch operation and stores the resultant target prefetched instruction in the L1 cache. If a demand load arrives, the processor analyzes the target prefetched instruction for effectiveness and determines the source of the prefetch data. If a demand does not arrive, the processor tests to determine if the particular prefetched instruction timed out in the cache and identifies the ineffectiveness of the prefetch operation. The processor samples multiple prefetch operations at random and generates a history of prefetch effectiveness and other useful prefetch information. The processor stores the prefetch effectiveness information to enable reduction or removal of ineffective prefetch operations.

Abstract: A processor of an information handling system (IHS) initiates an L3 cache prefetch operation in response to a demand load during instruction processing. The processor selects an L3 cache prefetch at random for tracking as a target prefetched instruction. The processor initiates an L1 cache target prefetch operation and stores the resultant target prefetched instruction in the L1 cache. If a demand load arrives, the processor analyses the target prefetched instruction for effectiveness and determines the source of the prefetch data. If a demand does not arrive, the processor tests to determine if the particular prefetched instruction timed out in the cache and identifies the infectiveness of the prefetch operation. The processor samples multiple prefetch operations at random and generates a history of prefetch effectiveness and other useful prefetch information. The processor stores the prefetch effectiveness information to enable reduction or removal of ineffective prefetch operations.

Abstract: Detecting and recording events in a processor with a performance monitor in the processor that samples events. The performance monitor in the processor receives performance event signals generated by the processor that indicate the current full event state of the processor. A limited number of counters are provided in the performance monitor for counting only a selected subset of the performance event signals. An event register is provided in the performance monitor that intercepts the performance event signals prior to the subset of the performance event signals being counted. The performance event signals are stored together as a single unit in the event register. The unit is a full set of available performance event signals that indicate the current full event state of the processor.

Abstract: Detecting and recording events in a processor with a performance monitor in the processor that samples events. The performance monitor in the processor receives performance event signals generated by the processor that indicate the current full event state of the processor. A limited number of counters are provided in the performance monitor for counting only a selected subset of the performance event signals. An event register is provided in the performance monitor that intercepts the performance event signals prior to the subset of the performance event signals being counted. The performance event signals are stored together as a single unit in the event register. The unit is a full set of available performance event signals that indicate the current full event state of the processor.

Abstract: A method for detecting and recording events in a processor. A performance monitor in the processor receives performance event signals generated by the processor that indicate the current full event state of the processor. A limited number of counters are provided in the performance monitor for counting only a selected subset of the performance event signals. An event register is provided in the performance monitor that intercepts the performance event signals prior to the subset of the performance event signals being counted. The performance event signals are stored together as a single unit in the event register. The unit is a full set of available performance event signals that indicate the current full event state of the processor.

Abstract: A method, apparatus, and computer program product are disclosed for sampling all performance event signals generated by a processor. A performance monitor is included in the processor. The performance monitor receives performance event signals from the processor. These performance event signals indicate the current full event state of the processor. A limited number of counters are provided in the performance monitor for counting only a selected subset of the performance event signals. An event register is provided in the performance monitor that intercepts the performance event signals prior to the subset of the performance event signals being counted. The performance event signals are stored together as a single unit in the event register. The unit is a full set of available performance event signals that indicate the current full event state of the processor.

Abstract: A method, system and apparatus for instruction execution tracing with out of order speculative processors. Information corresponding to the state of an instruction cache and a data cache is stored in a trace storage device along with information corresponding to instructions sequenced and executed by the processor. When a cache load is necessary, updated cache information is stored in the trace storage device. Thereby, the state of the cache at all times during execution of instructions may be known from the information stored in the trace storage device. Additionally, the particular instructions sequenced and executed is known from the sequenced instructions information and the executed instructions information stored in the trace storage device. Hence the instruction execution stream may be reconstructed from the information stored in the trace storage device.