Abstract: A method, apparatus and product useful for verifying Distributed Symmetric Multi-Processing systems (DSMPs). The method comprising: determining one or more sub-systems of a DSMP, wherein each sub-system is a Symmetric Multi-Processing System (SMP) which comprises a shared memory and a set of processing entities that have the same access permissions to the shared memory; and verifying the DSMP using a verification tool designed to verify an SMP, wherein said verifying is performed by verifying each sub-system.

Abstract: A method, apparatus and product useful for verifying Distributed Symmetric Multi-Processing systems (DSMPs). The method comprising: determining one or more sub-systems of a DSMP, wherein each sub-system is a Symmetric Multi-Processing System (SMP) which comprises a shared memory and a set of processing entities that have the same access permissions to the shared memory; and verifying the DSMP using a verification tool designed to verify an SMP, wherein said verifying is performed by verifying each sub-system.

Abstract: A test generator generating a test for a system having a plurality of executing entities that are capable of concurrent execution, the test comprises transactions that comprise one or more access transactions that are configured to access a shared resource and one or more reconfiguration transactions configured that are configured to reconfigure the shared resource, wherein said generating comprises: determining a partial order between pairs of transactions that are both associated with the shared resource and that at least one of which is a reconfiguration transaction; and generating the test so as to enforce the partial order during execution of the test by the system.

Abstract: A method, apparatus and product useful for verifying Distributed Symmetric Multi-Processing systems (DSMPs). The method comprising: determining one or more sub-systems of a DSMP, wherein each sub-system is a Symmetric Multi-Processing System (SMP) which comprises a shared memory and a set of processing entities that have the same access permissions to the shared memory; and verifying the DSMP using a verification tool designed to verify an SMP, wherein said verifying is performed by verifying each sub-system.

Abstract: A method comprising using at least one hardware processor for: providing a plurality of behavioral models of vehicular components; providing a plurality of simulated vehicular components; providing a model of interaction between at least some of said vehicular components; and generating a simulation test for said vehicular components by defining continuous behavioral functions for said plurality of behavioral models and for said plurality of simulated vehicular components, wherein each of said continuous behavioral functions comprises a superimposition of a finite number of continuous functions each having a finite number of parameters, and wherein at least some of said continuous behavioral functions interrelate in accordance with said model of interaction.

Abstract: A test generator generating a test for a system having a plurality of executing entities that are capable of concurrent execution, the test comprises transactions that comprise one or more access transactions that are configured to access a shared resource and one or more reconfiguration transactions configured that are configured to reconfigure the shared resource, wherein said generating comprises: determining a partial order between pairs of transactions that are both associated with the shared resource and that at least one of which is a reconfiguration transaction; and generating the test so as to enforce the partial order during execution of the test by the system.

Abstract: A system-level testcase may be generated by performing system-level generation tasks by a system-level generator to produce an abstract testcase. Based upon the abstract testcase, one or more unit-level generators may generate the testcase. The testcase may be utilized in simulation of operation of a system-under-test (SUT). The testcase may be utilized for verification of the SUT. The SUT may comprise a plurality of units. The unit-level generator may be associated with units of the SUT and perform generation tasks associated with pertinent units.

Abstract: A method, apparatus and product useful for verifying Distributed Symmetric Multi-Processing systems (DSMPs). The method comprising: determining one or more sub-systems of a DSMP, wherein each sub-system is a Symmetric Multi-Processing System (SMP) which comprises a shared memory and a set of processing entities that have the same access permissions to the shared memory; and verifying the DSMP using a verification tool designed to verify an SMP, wherein said verifying is performed by verifying each sub-system.

Abstract: Test template may comprise a source code template instruction associated with source code commands. The source code template instruction is utilized in generation of a test. The generation of instructions associated with the source code template instruction takes into account utilization of shared resources by both the source code commands and by generated instructions that are generated by other template instructions.

Abstract: A system-level testcase may be generated by performing system-level generation tasks by a system-level generator to produce an abstract testcase. Based upon the abstract testcase, one or more unit-level generators may generate the testcase. The testcase may be utilized in simulation of operation of a system-under-test (SUT). The testcase may be utilized for verification of the SUT. The SUT may comprise a plurality of units. The unit-level generator may be associated with units of the SUT and perform generation tasks associated with pertinent units.

Abstract: A test template comprising a repetitive block instruction is translated to a stimuli to be used by a target computerized system or a simulator of such a system. The translation comprises reusing translated portion of the repetitive block instruction in order to reduce translation time and to hasten testing phase of the target computerized system. Reuse may be affected by subcomponents of the target computerized system, a predetermined minimal or maximal number of instructions to reuse, and a heuristic determination to increase possibility of discovering a bug using the stimuli.

Abstract: Test template may comprise a source code template instruction associated with source code commands. The source code template instruction is utilized in generation of a test. The generation of instructions associated with the source code template instruction takes into account utilization of shared resources by both the source code commands and by generated instructions that are generated by other template instructions.

Abstract: A test template comprising a repetitive block instruction is translated to a stimuli to be used by a target computerized system or a simulator of such a system. The translation comprises reusing translated portion of the repetitive block instruction in order to reduce translation time and to hasten testing phase of the target computerized system. Reuse may be affected by subcomponents of the target computerized system, a predetermined minimal or maximal number of instructions to reuse, and a heuristic determination to increase possibility of discovering a bug using the stimuli.

Abstract: Some demonstrative embodiments of the invention may include, for example, devices, systems and methods of performing functional verification of a hardware design. In some demonstrative embodiments, a test generator may include a transaction generator to automatically generate a plurality of manipulated transactions by manipulating one or more test case transactions resulting from a constraint-satisfaction-problem.

Abstract: Some demonstrative embodiments of this invention may include, for example, devices, systems and methods of performing functional verification of a hardware design. In some demonstrative embodiments, a test generator may include a transaction generator to automatically generate a plurality of manipulated transactions by manipulating one or more test case transactions resulting from a constraint-satisfaction-problem. Other embodiments are described and claimed.