Abstract: A method is provided for calibrating a test system, including first and second test instruments. The method includes connecting a first test port of the first test instrument to a second test port of the second test instrument; generating a first RF signal using a first RF source of the first test instrument while a second RF source of the second test instrument is turned off; measuring first phase of the first RF signal at the first test port using first incident and reflected signals; generating a second RF signal using a second RF source of the second test instrument while the first RF source; measuring second phase of the second RF signal at the first test port using the second incident signal and reflected signals; determining a phase difference between the first and second phases; and adjusting the first and/or second RF source to remove the determined phase difference.

Abstract: A variable frequency multiplier circuit for frequency multiplying an input signal provided by an ultra-low phase noise signal source includes a tone generator configured to generate a multiple tones from the input signal; a signal separating circuit configured to separate the multiple tones into tones of interest and idler tones, where the tones of interest are separated into one or more groups and outputted from the signal separating circuit, and the idler tones are terminated; an amplification circuit configured to amplify each group of the tones of interest to optimize small and large signal responses; and a switched filter bank configured to selectively connect a selected tone from the tones of interest to a circuit output.

Abstract: A method is provided for calibrating a test system, including first and second test instruments. The method includes connecting a first test port of the first test instrument to a second test port of the second test instrument; generating a first RF signal using a first RF source of the first test instrument while a second RF source of the second test instrument is turned off; measuring first phase of the first RF signal at the first test port using first incident and reflected signals; generating a second RF signal using a second RF source of the second test instrument while the first RF source; measuring second phase of the second RF signal at the first test port using the second incident signal and reflected signals; determining a phase difference between the first and second phases; and adjusting the first and/or second RF source to remove the determined phase difference.

Abstract: A method is provided for calibrating a test system, including an RF source combined with a VNA connected to or embedded in a test instrument. The method includes connecting to a power meter at the test port; generating an RF signal at an RF source as an incident signal, and providing the incident signal to the power meter through the test port; measuring a forward power wave of the incident signal using a first receiver; measuring a reverse power wave of a reflected signal using a second receiver; measuring output power at the test port using the power meter; and calculating magnitude errors of the first receiver and the second receiver using the measured forward power wave, the measured reverse power wave, and the measured output power by the power meter, and determining magnitude error correction terms of the forward and reverse power waves to remove the magnitude errors.

Abstract: A test instrument, including an embedded VNA circuit, for testing a DUT. The test instrument includes a first receiver for receiving an incident RF signal through a first coupling device; a second receiver for receiving a reflected RF signal through a second coupling device; a test port for connecting to an interconnect, which is connectable to a calibration device in a calibrating stage, during which the interconnect is characterized, and to the DUT in a testing stage, during which at least one parameter of the DUT is tested; an RF source for generating the incident RF signal during the calibrating stage; and a processing unit programmed to determine S-parameters of the interconnect based on the incident RF signal and the reflected RF signal, the S-parameters compensating for error introduced by the interconnect when testing the at least one parameter of the DUT in the testing stage.

Abstract: A method is provided for calibrating a test system, including an RF source combined with a VNA connected to or embedded in a test instrument. The method includes connecting to a power meter at the test port; generating an RF signal at an RF source as an incident signal, and providing the incident signal to the power meter through the test port; measuring a forward power wave of the incident signal using a first receiver; measuring a reverse power wave of a reflected signal using a second receiver; measuring output power at the test port using the power meter; and calculating magnitude errors of the first receiver and the second receiver using the measured forward power wave, the measured reverse power wave, and the measured output power by the power meter, and determining magnitude error correction terms of the forward and reverse power waves to remove the magnitude errors.

Abstract: A test instrument, including an embedded VNA circuit, for testing a DUT. The test instrument includes a first receiver for receiving an incident RF signal through a first coupling device; a second receiver for receiving a reflected RF signal through a second coupling device; a test port for connecting to an interconnect, which is connectable to a calibration device in a calibrating stage, during which the interconnect is characterized, and to the DUT in a testing stage, during which at least one parameter of the DUT is tested; an RF source for generating the incident RF signal during the calibrating stage; and a processing unit programmed to determine S-parameters of the interconnect based on the incident RF signal and the reflected RF signal, the S-parameters compensating for error introduced by the interconnect when testing the at least one parameter of the DUT in the testing stage.