Abstract: An analog neuromphric circuit is disclosed having an input layer, a liquid layer, and an output layer each with resistive memory crossbar configurations to identify a temporal signal for a duration of time. The input layer encodes input layer spiking neurons based on encoding signals generated from input voltages applied an input layer resistive memory crossbar configuration. The liquid layer counts each spike generated by liquid layer spiking neurons for the duration of time based on liquid layer signals generated from the input spiking neuron voltages generated from each input layer spiking neurons applied to a liquid layer resistive memory crossbar configuration. The output layer identifies the temporal signal for the duration of time based on output voltages generated from the counting voltages generated from each count of each spike generated by the liquid layer spiking neurons for the duration of time applied to an output resistive memory crossbar configuration.

Abstract: Systems and methods are provided for triggering delayed transaction processing when certain transaction gateway problems are detected across a number of transactions. To complete a given transaction, a processing system may coordinate transfer of funds in a manner that includes communications among multiple third-party systems, such as a tokenization service or token vault, a payment gateway, and a bank or credit card processor. When there are connectivity or other problems with one of these other systems, a system and associated methods are provided for selectively delaying a subset of transactions while still providing some assurance to the transaction requestor and recipient that the transaction will proceed.

Abstract: Apparatus and system that perform the method of providing a FCoE Transformer including an Ethernet Interface and a Fibre Channel Interface, receiving, at the FCoE Transformer, an FCoE Frame via a Layer 2 Ethernet Switch, converting, at the FCoE Transformer, the FCoE Frame to a Fibre Channel Frame. The FCoE Frame includes a SOF field included in an FCoE Transport Header for providing an SOF character used to start the fibre channel frame, and the SOF field in the FCoE Transport Header is for encoding the SOF field, Fibre Channel Frame. The FCoE Frame includes an EOF field included in an FCoE Transport Header for providing an EOF character used to end the fibre channel frame, and the EOF field in the FCoE Transport Header is for encoding the EOF field, Fibre Channel Frame. The method includes transporting the Fibre Channel Frame.

Abstract: Apparatus and system for performing the method of providing a FCoE HBA including a Virtual Fibre Channel Port and an Ethernet Interface, providing a Layer 2 Ethernet Switch, and sending an FCoE Frame via the Layer 2 Ethernet Switch. The FCoE Frame includes a SOF field included in an FCoE Transport Header for providing an SOF character used to start a Fibre Channel Frame, and the SOF field in the FCoE Transport Header is for encoding the SOF field, Fibre Channel Frame. The FCoE Frame includes an EOF field included in an FCoE Transport Header for providing an EOF character used to end the Fibre Channel Frame, and the EOF field in the FCoE Transport Header is for encoding the EOF field, Fibre Channel Frame.

Abstract: Methods and apparatus for the Transporting of Fibre Channel data over Ethernet are disclosed. In one embodiment of the invention, a server (32) contains a virtual Fibre Channel Host Bus Adapter (HBA) (40). The virtual Fibre Channel HBA (40) contains a number of virtual Fibre Channel N-Ports (42) and an Ethernet interface (44). The virtual Fibre Channel HBA (40) is connected to an Ethernet layer (2) switch (24) via an ethernet local area network (21). The Ethernet layer (2) switch (24) is also connected to an FCoE Transformer (46) via an ethernet local area network (21). The FCoE Transformer (46) is connected to the Fibre Channel storage area network (20). Contained within the FCoE Transformer (46) are a number of real Fibre Channel N-Ports (48) that correspond to the virtual Fibre Channel N-Ports (42).

Abstract: Methods and apparatus for the Transporting of Fibre Channel data over Ethernet are disclosed. In one embodiment of the invention, a server (32) contains a virtual Fibre Channel Host Bus Adapter (HBA) (40). The virtual Fibre Channel HBA (40) contains a number of virtual Fibre Channel N-Ports (42) and an Ethernet interface (44). The virtual Fibre Channel HBA (40) is connected to an Ethernet layer (2) switch (24) via an ethernet local area network (21). The Ethernet layer (2) switch (24) is also connected to an FCoE Transformer (46) via an ethernet local area network (21). The FCoE Transformer (46) is connected to the Fibre Channel storage area network (20). Contained within the FCoE Transformer (46) are a number of real Fibre Channel N-Ports (48) that correspond to the virtual Fibre Channel N-Ports (42).

Abstract: Systems and methods are provided for triggering delayed transaction processing when certain transaction gateway problems are detected across a number of transactions. To complete a given transaction, a processing system may coordinate transfer of funds in a manner that includes communications among multiple third-party systems, such as a tokenization service or token vault, a payment gateway, and a bank or credit card processor. When there are connectivity or other problems with one of these other systems, a system and associated methods are provided for selectively delaying a subset of transactions while still providing some assurance to the transaction requestor and recipient that the transaction will proceed.

Abstract: A storage appliance includes: control circuitry; a plurality of storage communication ports; and switch circuitry configured to forward packets compliant with a storage protocol to identified ones of the plurality of storage communication ports. In an aspect, a memory supports a forwarding table or tables. The apparatus can implement storage appliance operations by division of the storage appliance operations into (i) data movement operations performed by the switch circuitry instead of the general processor circuitry and (ii) general computation operations performed by the switch circuitry instead of the general processor circuitry.

Abstract: Enhancing growth of algae in an algaculture facility includes contacting a growth medium with a gas including carbon dioxide, transferring some of the carbon dioxide to the growth medium to yield an enriched growth medium, and providing the enriched growth medium to the algaculture facility. The concentration of dissolved carbon dioxide in the enriched growth medium exceeds the concentration of dissolved carbon dioxide in the growth medium, where dissolved carbon dioxide includes ions formed by the reaction of carbon dioxide with a species in solution. The growth medium may be obtained from the algaculture facility, and may be filtered or otherwise processed before or after contacting the growth medium with the gas. Providing the enriched growth medium to the algaculture facility increases the concentration of dissolved carbon dioxide in the bulk growth medium of the algaculture facility.

Abstract: Capturing a target gas includes contacting a gas mixture including a target species with an aqueous solution including a buffer species, and transferring some of the target species from the gas mixture to the aqueous solution. The target species forms a dissolved target species in the aqueous solution, and the aqueous solution is processed to yield a first aqueous stream and a second aqueous stream, where the equilibrium partial pressure of the target species over the second aqueous stream exceeds the equilibrium partial pressure of the target species over the first aqueous stream. At least some of the dissolved target species in the second aqueous stream is converted to the target species, and the target species is liberated from the second aqueous stream. The target species can be collected and/or compressed for subsequent processing or use.

Abstract: Capturing a target gas includes contacting a gas mixture including a target species with an aqueous solution including a buffer species, and transferring some of the target species from the gas mixture to the aqueous solution. The target species forms a dissolved target species in the aqueous solution, and the aqueous solution is processed to yield a first aqueous stream and a second aqueous stream, where the equilibrium partial pressure of the target species over the second aqueous stream exceeds the equilibrium partial pressure of the target species over the first aqueous stream. At least some of the dissolved target species in the second aqueous stream is converted to the target species, and the target species is liberated from the second aqueous stream. The target species can be collected and/or compressed for subsequent processing or use.

Abstract: This invention provides means and methods for improving the routing and multiplexing logic of microprocessor busses and other similar high fan logic functions in FPGA and ASIC circuits. Routing of high fan-in signals is simplified by distributing the multiplexing function. The multiplexing function is separated into an AND function in the logic block and a programmable OR function in the routing block. Programming bits control which signals are ORed together in the routing elements. The AND output of a peripheral is controlled by either a distributed control circuit or by control signal(s) from a centralized control circuit.

Abstract: A router system, method and computer program product are provided. In use, it is determined whether a flow associated with a received packet is new. If it is determined that the flow associated with the packet is new, at least a portion of the packet is routed utilizing a first module. If, on the other hand, it is determined that the flow associated with the packet is not new, at least a portion of the packet is routed or switched utilizing a second module that costs at least 10 times less than the first module.

Abstract: A system, method and computer program product are provided. In use, a plurality of flows associated with packets destined for an output port is identified. A utilization associated with the output port is further measured. Thus, rates of a plurality of the flows destined for the output port may be individually controlled at an input port thereof, based on the utilization to ensure that the utilization remains less than 99.9% and avoid buffering more than 400 packets with a correspondingly low delay.

Abstract: A hardware or software apparatus, or a combination of both, is used for efficiently managing the dynamic allocation, access and release of memory used in a computational environment. This apparatus reduces, or preferably eliminates, the requirements for application housekeeping, such as garbage collection, by providing substantially more deterministic dynamic memory management operations. Housekeeping, or garbage collection, such as memory compaction and unused space retrieval, are reduced or eliminated. When housekeeping is eliminated, all dynamic memory invocations become substantially deterministic. The invention maps all or a part of a large, sparsely populated logical memory address space used to store dynamically allocated objects, to a smaller, denser physical memory address space.