Patents by Inventor Alex Kai Hung See
Alex Kai Hung See has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9230886Abstract: Semiconductor devices with through silicon vias (TSVs) are formed without copper contamination. Embodiments include exposing a passivation layer surrounding a bottom portion of a TSV in a silicon substrate, forming a silicon composite layer over the exposed passivation layer and over a bottom surface of the silicon substrate, forming a hardmask layer over the silicon composite layer and over the bottom surface of the silicon substrate, removing a section of the silicon composite layer around the bottom portion of the TSV using the hardmask layer as a mask, re-exposing the passivation layer, and removing the hardmask layer and the re-exposed passivation layer to expose a contact for the bottom portion of the TSV.Type: GrantFiled: December 18, 2014Date of Patent: January 5, 2016Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Lup San Leong, Zheng Zou, Alex Kai Hung See, Hai Cong, Xuesong Rao, Yun Ling Tan, Huang Liu
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Publication number: 20150137359Abstract: Semiconductor devices with through silicon vias (TSVs) are formed without copper contamination. Embodiments include exposing a passivation layer surrounding a bottom portion of a TSV in a silicon substrate, forming a silicon composite layer over the exposed passivation layer and over a bottom surface of the silicon substrate, forming a hardmask layer over the silicon composite layer and over the bottom surface of the silicon substrate, removing a section of the silicon composite layer around the bottom portion of the TSV using the hardmask layer as a mask, re-exposing the passivation layer, and removing the hardmask layer and the re-exposed passivation layer to expose a contact for the bottom portion of the TSV.Type: ApplicationFiled: December 18, 2014Publication date: May 21, 2015Inventors: Lup San LEONG, Zheng ZOU, Alex Kai Hung SEE, Hai CONG, Xuesong RAO, Yun Ling TAN, Huang LIU
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Patent number: 9034720Abstract: A method and a device are provided for diffracting incident light from a lithographic scanner in an IC process flow. Embodiments include forming a diffraction grating in a first layer on a semiconductor substrate; and forming a plurality of lithographic alignment marks in a second layer, overlying the first layer, wherein the diffraction grating has a width and a length greater than or equal to a width and length, respectively, of the plurality of lithographic alignment marks.Type: GrantFiled: August 17, 2012Date of Patent: May 19, 2015Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Hui Liu, Wen Zhan Zhou, Zheng Zou, Qun Ying Lin, Alex Kai Hung See
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Patent number: 8940637Abstract: Semiconductor devices with through silicon vias (TSVs) are formed without copper contamination. Embodiments include exposing a passivation layer surrounding a bottom portion of a TSV in a silicon substrate, forming a silicon composite layer over the exposed passivation layer and over a bottom surface of the silicon substrate, forming a hardmask layer over the silicon composite layer and over the bottom surface of the silicon substrate, removing a section of the silicon composite layer around the bottom portion of the TSV using the hardmask layer as a mask, re-exposing the passivation layer, and removing the hardmask layer and the re-exposed passivation layer to expose a contact for the bottom portion of the TSV.Type: GrantFiled: July 5, 2012Date of Patent: January 27, 2015Assignee: Globalfoundries Singapore Pte. Ltd.Inventors: Lup San Leong, Zheng Zou, Alex Kai Hung See, Hai Cong, Xuesong Rao, Yun Ling Tan, Huang Liu
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Publication number: 20140050439Abstract: A method and a device are provided for diffracting incident light from a lithographic scanner in an IC process flow. Embodiments include forming a diffraction grating in a first layer on a semiconductor substrate; and forming a plurality of lithographic alignment marks in a second layer, overlying the first layer, wherein the diffraction grating has a width and a length greater than or equal to a width and length, respectively, of the plurality of lithographic alignment marks.Type: ApplicationFiled: August 17, 2012Publication date: February 20, 2014Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Hui LIU, Wen Zhan Zhou, Zheng Zou, Qun Ying Lin, Alex Kai Hung See
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Publication number: 20140008810Abstract: Semiconductor devices with through silicon vias (TSVs) are formed without copper contamination. Embodiments include exposing a passivation layer surrounding a bottom portion of a TSV in a silicon substrate, forming a silicon composite layer over the exposed passivation layer and over a bottom surface of the silicon substrate, forming a hardmask layer over the silicon composite layer and over the bottom surface of the silicon substrate, removing a section of the silicon composite layer around the bottom portion of the TSV using the hardmask layer as a mask, re-exposing the passivation layer, and removing the hardmask layer and the re-exposed passivation layer to expose a contact for the bottom portion of the TSV.Type: ApplicationFiled: July 5, 2012Publication date: January 9, 2014Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Lup San Leong, Zheng Zou, Alex Kai Hung See, Hai Cong, Xuesong Rao, Yun Ling Tan, Huang Liu
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Patent number: 8518775Abstract: A memory device is fabricated through the integration of embedded non-volatile memory (eNVM) with replacement metal gate (RMG) and high-k/metal gate (HKMG) modules. Embodiments include forming two substrate portions having upper surfaces at different heights, forming non-volatile gate stacks over the substrate portion with the lower upper surface, and forming high-voltage gate stacks and logic gate stacks over the other substrate portion. Embodiments include the upper surfaces of the non-voltage gate stacks, the high-voltage gate stacks, and the logic gate stacks being substantially coplanar.Type: GrantFiled: October 3, 2011Date of Patent: August 27, 2013Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Huang Liu, Alex Kai Hung See, Hai Cong, Zheng Zou
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Patent number: 8415236Abstract: A method for fabricating a semiconductor device is provided. The method comprises selectively forming a first layer over a first and second exposed portions of a substrate. The first and second exposed portions are of different sizes and are located adjacent to a first and second active devices. During the first layer formation, a gas mixture comprising first and second source gases that function as growth components for forming the first layer and a reactant gas that functions as an etching component for controlling selectivity of the first layer growth is provided. The reactant gas is different from the first and second source gases and one of first and second source gases forms the first layer at a faster rate over the first exposed portion as compared to the second exposed portion and the other source gas exhibits an opposite behavior.Type: GrantFiled: December 29, 2009Date of Patent: April 9, 2013Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Han Guan Chew, Jinping Liu, Alex Kai Hung See, Mei Sheng Zhou
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Publication number: 20130082318Abstract: A memory device is fabricated through the integration of embedded non-volatile memory (eNVM) with replacement metal gate (RMG) and high-k/metal gate (HKMG) modules. Embodiments include forming two substrate portions having upper surfaces at different heights, forming non-volatile gate stacks over the substrate portion with the lower upper surface, and forming high-voltage gate stacks and logic gate stacks over the other substrate portion. Embodiments include the upper surfaces of the non-voltage gate stacks, the high-voltage gate stacks, and the logic gate stacks being substantially coplanar.Type: ApplicationFiled: October 3, 2011Publication date: April 4, 2013Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Huang Liu, Alex Kai Hung See, Hai Cong, Zheng Zou
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Publication number: 20120273949Abstract: Semiconductor devices are formed with a Cu or Cu alloy interconnect encapsulated by a substantially uniform MnO or Al2O3 layer. Embodiments include forming an opening having side surfaces and a bottom surface in a dielectric layer, forming a barrier layer on the side surfaces and the bottom surface of the opening and on an upper surface of the dielectric layer, treating the barrier layer with an oxygen plasma to form dangling oxygen atoms on the barrier layer, depositing a seed layer on the barrier layer, and filling the opening with Cu or a Cu alloy.Type: ApplicationFiled: April 27, 2011Publication date: November 1, 2012Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Huang Liu, Chim Seng Seet, Alex Kai Hung See
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Publication number: 20100167505Abstract: A method for fabricating a semiconductor device is provided. The method comprises selectively forming a first layer over a first and second exposed portions of a substrate. The first and second exposed portions are of different sizes and are located adjacent to a first and second active devices. During the first layer formation, a gas mixture comprising first and second source gases that function as growth components for forming the first layer and a reactant gas that functions as an etching component for controlling selectivity of the first layer growth is provided. The reactant gas is different from the first and second source gases and one of first and second source gases forms the first layer at a faster rate over the first exposed portion as compared to the second exposed portion and the other source gas exhibits an opposite behavior.Type: ApplicationFiled: December 29, 2009Publication date: July 1, 2010Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.Inventors: Han Guan CHEW, Jinping LIU, Alex Kai Hung SEE, Mei Sheng ZHOU
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Patent number: 6780691Abstract: A method for forming a transistor having an elevated source/drain structure is described. A gate electrode is formed overlying a substrate and isolated from the substrate by a gate dielectric layer. Isolation regions are formed in and on the substrate wherein the isolation regions have a stepped profile wherein an upper portion of the isolation regions partly overlaps and is offset from a lower portion of the isolation regions in the direction away from the gate electrode. Ions are implanted into the substrate between the gate electrode and the isolation regions to form source/drain extensions. Dielectric spacers are formed on sidewalls of the gate electrode and the isolation regions.Type: GrantFiled: August 16, 2002Date of Patent: August 24, 2004Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Randall Cher Liang Cha, Yeow Kheng Lim, Alex Kai Hung See, Jia Zhen Zheng
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Publication number: 20040033668Abstract: A method for forming a transistor having an elevated source/drain structure is described. A gate electrode is formed overlying a substrate and isolated from the substrate by a gate dielectric layer. Isolation regions are formed in and on the substrate wherein the isolation regions have a stepped profile wherein an upper portion of the isolation regions partly overlaps and is offset from a lower portion of the isolation regions in the direction away from the gate electrode. Ions are implanted into the substrate between the gate electrode and the isolation regions to form source/drain extensions. Dielectric spacers are formed on sidewalls of the gate electrode and the isolation regions.Type: ApplicationFiled: August 16, 2002Publication date: February 19, 2004Applicant: Chartered Semiconductor Manufacturing Ltd.Inventors: Randall Cher Liang Cha, Yeow Kheng Lim, Alex Kai Hung See, Jia Zhen Zheng