Patents by Inventor Alex Kalnitsky

Alex Kalnitsky has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • POWER DEVICES HAVING REDUCED ON-RESISTANCE AND METHODS OF THEIR MANUFACTURE
    Publication number: 20110156217
    Abstract: A method for forming a support structure for supporting and handling a semiconductor wafer containing vertical FETs formed at the front surface thereof is provided. In one embodiment, a semiconductor wafer is provided having a front surface and a rear surface, wherein the front surface comprises one or more dies separated by dicing lines. The wafer is thinned to a predetermined thickness. A plurality of patterned metal features are formed on a thinned rear surface to provide support for the wafer, wherein each of the plurality of patterned metal features covers substantially one die, leaving the dicing lines substantially uncovered. The wafer is thereafter diced along the dicing lines to separate the one or more dies for later chip packaging.
    Type: Application
    Filed: December 31, 2009
    Publication date: June 30, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Alex Kalnitsky, Hsiao-Chin Tuan, Liang-Kai Han, Uway Tseng, Yuan-Chih Hsieh, Hung-Hua Lin
  • Enhanced planarization technique for an integrated circuit
    Patent number: 5986330
    Abstract: A method for planarizing integrated circuit topographies, wherein, after a first layer of spin-on glass is deposited, a layer of low-temperature oxide is deposited before a second layer of spin-on glass.
    Type: Grant
    Filed: January 15, 1998
    Date of Patent: November 16, 1999
    Assignee: STMicroelectronics, Inc.
    Inventors: Alex Kalnitsky, Yih-Shung Lin
  • Enhanced planarization technique for an integrated circuit
    Patent number: 5837613
    Abstract: A method for planarizing integrated circuit topographies, wherein, after a first layer of spin-on glass is deposited, a layer of low-temperature oxide is deposited before a second layer of spin-on glass.
    Type: Grant
    Filed: November 24, 1997
    Date of Patent: November 17, 1998
    Assignee: STMicroelectronics, Inc.
    Inventors: Alex Kalnitsky, Yih-Shung Lin
  • Integrated circuit with enhanced planarization
    Patent number: 5633534
    Abstract: A method for planarizing integrated circuit topographies, wherein, after a first layer of spin-on glass is deposited, a layer of low-temperature oxide is deposited before a second layer of spin-on glass.
    Type: Grant
    Filed: July 15, 1996
    Date of Patent: May 27, 1997
    Assignee: SGS-Thomson Microelectronics, Inc.
    Inventors: Alex Kalnitsky, Yih-Shung Lin
  • Enhanced planarization technique for an integrated circuit
    Patent number: 5435888
    Abstract: A method for planarizing integrated circuit topographies, wherein, after a first layer of spin-on glass is deposited, a layer of low-temperature oxide is deposited before a second layer of spin-on glass.
    Type: Grant
    Filed: December 6, 1993
    Date of Patent: July 25, 1995
    Assignee: SGS-Thomson Microelectronics, Inc.
    Inventors: Alex Kalnitsky, Yih-Shung Lin
  • Enhanced planarization technique for an integrated circuit
    Patent number: RE39690
    Abstract: A method for planarizing integrated circuit topographies, wherein, after a first layer of spin-on glass is deposited, a layer of low-temperature oxide is deposited before a second layer of spin-on glass.
    Type: Grant
    Filed: November 16, 2001
    Date of Patent: June 12, 2007
    Assignee: STMicroelectronics, Inc.
    Inventors: Alex Kalnitsky, Yih-Shung Lin