Abstract: Embodiments related to fetching instructions and alternate versions achieving the same functionality as the instructions from an instruction cache included in a microprocessor are provided. In one example, a method is provided, comprising, at an example microprocessor, fetching an instruction from an instruction cache. The example method also includes hashing an address for the instruction to determine whether an alternate version of the instruction which achieves the same functionality as the instruction exists. The example method further includes, if hashing results in a determination that such an alternate version exists, aborting fetching of the instruction and retrieving and executing the alternate version.

Abstract: An apparatus and method are provided for transferring a plurality of data structures between memory and a plurality of vector registers, each vector register being arranged to store a vector operand comprising a plurality of data elements. Access circuitry is used to perform access operations to move data elements of vector operands between the data structures in memory and specified vector registers, each data structure comprising multiple data elements stored at contiguous addresses in the memory.

Abstract: An apparatus and method are provided for transferring a plurality of data structures between memory and a plurality of vector registers, each vector register being arranged to store a vector operand comprising a plurality of data elements. Access circuitry is used to perform access operations to move data elements of vector operands between the data structures in memory and specified vector registers, each data structure comprising multiple data elements stored at contiguous addresses in the memory.

Abstract: A dual ported replicated data cache. The cache is configured for storing input data blocks. The cache includes an augmenter for producing an augmented data block with parity information from the input data block, a first memory array for storing the augmented data block, and a second memory array for storing the augmented data block.

Abstract: Embodiments related to fetching instructions and alternate versions achieving the same functionality as the instructions from an instruction cache included in a microprocessor are provided. In one example, a method is provided, comprising, at an example microprocessor, fetching an instruction from an instruction cache. The example method also includes hashing an address for the instruction to determine whether an alternate version of the instruction which achieves the same functionality as the instruction exists. The example method further includes, if hashing results in a determination that such an alternate version exists, aborting fetching of the instruction and retrieving and executing the alternate version.

Abstract: A method for tagging cache entries to support context switching for virtual machines and for operating systems. The method includes, storing a plurality of entries within a cache of a CPU of a computer system, wherein each of the entries includes a context ID, handling a first portion of the entries as local entries when the respective context IDs indicate a local status, and handling a second portion of the entries as global entries when the respective context IDs indicate a global status.

Abstract: A dual ported replicated data cache. The cache is configured for storing input data blocks. The cache includes an augmenter for producing an augmented data block with parity information from the input data block, a first memory array for storing the augmented data block, and a second memory array for storing the augmented data block.

Abstract: A dual ported replicated data cache. The cache is configured for storing input data blocks. The cache includes an augmenter for producing an augmented data block with parity information from the input data block, a first memory array for storing the augmented data block, and a second memory array for storing the augmented data block.

Abstract: A method and apparatus for breaking complex X86 segment operations and segmented memory addressing into explicit sub-operations so that they may be exposed to compiler or translator-based optimizations.

Abstract: A method and apparatus for breaking complex X86 segment operations and segmented addressing into explicit sub-operations so that they may be exposed to compiler or translator-based optimizations.

Abstract: A method and apparatus for breaking complex X86 segment operations and segmented memory addressing into explicit sub-operations so that they may be exposed to compiler or translator-based optimizations. A method includes providing a first segment selector for deriving a linear address of a segment descriptor in a first descriptor table and providing a second segment selector for deriving a linear address of a segment descriptor in a second descriptor table. The method also includes attempting an access of the first descriptor table to derive a segment descriptor, and if the access of the first descriptor table fails, attempting an access of the second descriptor table to derive a segment descriptor. The method also includes storing a derived segment descriptor from a successful attempted access in a descriptor register.

Abstract: A floating point processor including a plurality of explicitly-addressable processor registers, an emulation register capable of storing a value used to logically rename the explicitly-addressable registers to emulate registers of a floating point stack, a computer-executable software process for calculating and changing a value in the emulation register to a value indicating a change in addresses of registers of a floating point stack when executing a floating point stack operation, and adder circuitry combining a register address and the value in the emulation register in response to the computer-executable process to rename the plurality of explicitly-addressable processor registers.

Abstract: Apparatus and a method for generating an interrupt when a direct memory access by an I/O device is desired, suspending the operation of the microprocessor in response to the interrupt, placing state of the morph host to a last known correct state in response to the interrupt, determining the memory operation commanded by the I/O device, and utilizing the microprocessor to execute the memory operation commanded by the I/O device.

Abstract: A method and apparatus for breaking complex X86 segment operations and segmented addressing into explicit sub-operations so that they may be exposed to compiler or translator-based optimizations.

Abstract: A method for determining if writes to a memory page are directed to target instructions which have been translated to host instructions in a computer which translates instructions from a target instruction set to a host instruction set, including the steps of detecting a write to a memory page storing target instructions which have been translated to host instructions, detecting whether a sub-area of the memory page to which the write is addressed stores target instructions which have been translated, and invalidating host instructions translated from addressed target instructions.

Abstract: A computer implemented process for detecting errors in computer systems including the steps of executing sequences of instructions of a software program on each of a reference system and a test system, detecting and recording state of the reference system and the test system at comparable points in the execution of the program, and comparing the detected state of the reference system and the test system at selectable comparable points in the sequence of instructions including the end of the sequence of instructions. In a particular embodiment, the execution of portions of the sequence of instructions between selectable comparable points on each of the reference system and the test system is automatically replayed if a difference in compared state of the systems is detected.