Abstract: A method of synthesis of multiple implementations of a design is provided comprising: translating a model of the design to a first output model compliant with first constraints; and translating the model of the design to a second output model compliant with second constraints.

Abstract: A method of converting a Boolean logic circuit into an asynchronous multi-rail circuit is provided. A Boolean logic circuit is converted into a first multi-rail circuit using at least Shannon's expansion. The first multi-rail circuit is technology mapped into a second multi-rail circuit. Completion detection circuitry is added which receives the primary outputs of the second multi-rail circuit.

Abstract: A method of synthesis of multiple implementations of a design is provided comprising: translating a model of the design to a first output model compliant with first constraints; and translating the model of the design to a second output model compliant with second constraints.

Abstract: A method of synthesis of multiple implementations of a design is provided comprising: translating a model of the design to a first output model compliant with first constraints; and translating the model of the design to a second output model compliant with second constraints.

Abstract: A method of designing a skew insensitive circuit is performed by designing a synchronous circuit including flip-flops and combinatorial logic and, for each flip-flop, inserting logic gates to receive a skewed clock signal and to locally derive non-overlapping clock phases from the skewed clock signal.

Abstract: A method of synthesis of a model representing a design is provided comprising: inputting to a synthesis tool information representing a design at a level of abstraction; using a synthesis tool to automatically translate the information representing a design at a level of abstraction to a model representing the design at a lower level abstraction; and producing a record the information input to the tool representing the design at the level of abstraction.

Abstract: A method of converting a Boolean logic circuit into an asynchronous multi-rail circuit is provided. A Boolean logic circuit is converted into a first multi-rail circuit using at least Shannon's expansion. The first multi-rail circuit is technology mapped into a second multi-rail circuit. Completion detection circuitry is added which receives the primary outputs of the second multi-rail circuit.

Abstract: A method of producing multiple models of a hardware (integrated circuit) design including: translating a master model of a design of the integrated circuit to at least first and second models that are functionally equivalent to the master model and that are at different levels of abstraction from each, other and in which each of the first and second models includes integrated circuit timing information that is accurate for its level of abstraction.

Abstract: A method for analyzing a circuit design identifies a possible noise fault for a timing interval based on a timing analysis of a victim net and at least one aggressor net of the circuit design and determines whether the noise fault is feasible based on a behavioral representation of the victim net and the aggressor net for the timing interval.

Abstract: A method of synthesis of multiple implementations of a design is provided comprising: translating a model of the design to a first output model compliant with first constraints; and translating the model of the design to a second output model compliant with second constraints.

Abstract: A method of producing multiple models of a hardware (integrated circuit) design including: translating a master model of a design of the integrated circuit to at least first and second models that are functionally equivalent to the master model and that are at different levels of abstraction from each, other and in which each of the first and second models includes integrated circuit timing information that is accurate for its level of abstraction.

Abstract: A method of synthesis of a model representing a design is provided comprising: inputting to a synthesis tool information representing a design at a level of abstraction; using a synthesis tool to automatically translate the information representing a design at a level of abstraction to a model representing the design at a lower level abstraction; and producing a record the information input to the tool representing the design at the level of abstraction.

Abstract: A method for designing a multi-rail asynchronous circuit is provided. The method includes providing a circuit having n circuit paths, defining a plurality of nodes, each node having an n-rail signal output and at least one n-rail signal input, each rail of the n-rail signal input being connected to a different one of the plurality of circuit paths, and adding completeness detection to each of the plurality of nodes, completion detection for a downstream one of the plurality of nodes being at least partially based on completion detection from an upstream one of the plurality of nodes. Signals propagate along the plurality of data paths independent of the completeness detection.

Abstract: A method for designing a multi-rail asynchronous circuit is provided. The method includes providing a circuit having n circuit paths, defining a plurality of nodes, each node having an n-rail signal output and at least one n-rail signal input, each rail of the n-rail signal input being connected to a different one of the plurality of circuit paths, and adding completeness detection to each of the plurality of nodes, completion detection for a downstream one of the plurality of nodes being at least partially based on completion detection from an upstream one of the plurality of nodes. Signals propagate along the plurality of data paths independent of the completeness detection.