Abstract: A particle detector. The particle detector comprises one or more light sources, an optical sensor, and a controller. The one or more light sources are collectively operable to simultaneously produce at least two wavelength ranges of emitted light. The optical sensor is configured to sense light of the at least two wavelength ranges emitted by the one or more light sources and to distinguish each range. The controller is configured to detect particles based on the light sensed by the optical sensor.

Abstract: A power supply circuit includes a control switch, a synchronous switch, an inductor, and a voltage ramping circuit. A common node in the power supply serially connects the control switch to the synchronous switch. The common node is further coupled to the inductor that supplies current to a load based on switching the control switch and the synchronous switch to respective ON/OFF and OFF/ON states. The voltage ramping circuit generates and controls ramping of a gate voltage of the control switch based at least in part on a magnitude of a feedback voltage received on a circuit path from the common node. The multi-stage ramping of a switch control voltage reduces one or more of the following: i) QRR losses, ii) switching losses, and/or iii) a dead time of the power supply.

Abstract: A power supply circuit includes a control switch, a synchronous switch, an inductor, and a voltage ramping circuit. A common node in the power supply serially connects the control switch to the synchronous switch. The common node is further coupled to the inductor that supplies current to a load based on switching the control switch and the synchronous switch to respective ON/OFF and OFF/ON states. The voltage ramping circuit generates and controls ramping of a gate voltage of the control switch based at least in part on a magnitude of a feedback voltage received on a circuit path from the common node. The multi-stage ramping of a switch control voltage reduces one or more of the following: i) QRR losses, ii) switching losses, and/or iii) a dead time of the power supply.

Abstract: In one implementation, a power field-effect transistor (FET) having a reduced gate resistance includes a drain, a source, a gate, and a gate contact including a gate pad, a gate highway, and multiple gate buses. The gate buses are formed from a first metal layer having a first thickness, while the gate pad and the gate highway each include a metal stack including the first metal layer and a second metal layer. The second metal layer has a second thickness substantially greater than the first thickness, thereby reducing the gate resistance of the power FET.

Abstract: In one embodiment, the present disclosure includes an amplifier comprising first and second output stages. The first output stage receives first power supply voltages and the second output stage receives second power supply voltages greater than the first power supply voltages. A switching stage configures the output stages to provide a first current to an amplifier output node from the first output stage when a magnitude of a voltage on the output node is below a first value, provide a second current to the output node from the second output stage when the magnitude of the voltage on the output node is above a second value greater than the first value, and provide a third current to the output node from both the first output stage and the second output stage when the magnitude of the voltage on the output node is between the first value and the second value.