Abstract: A computer and a method are described having multiple pointers for a branch instruction. A branch target instruction called by the branch instruction is divided into H parts locatable by K pointers. L of the K pointers are stored in the branch instruction and K-L pointers are stored with the H parts of the branch target instruction. A tag identifies a variable boundary between first and second halves of the memory, word by word. The first half of the memory space contains V of H parts of the instructions and the second half of the memory space contains the H-V parts. The parts in the first and second halves of the memory space are compressed and decompressed in parallel.

Abstract: A computer system and method are described having a single pointer for a branch target instruction and multiple pointers and instruction parts for non-branch target instructions. All instructions, except branch target instructions are divided and stored in different location within a memory. A tag is used to identify a variable boundary between first and second halves of the memory space, word by word. The first half of the memory space contains V of H parts of the instructions and the second half of the memory space contains the H-V parts. The parts in the first and second halves of the memory space can be compressed and decompressed in parallel.

Abstract: A compiler system (190) stores a data structure (101, e.g., a program) to a memory (110) of an execution system (100). The data structure (101) comprises, for example, processor instructions coded by compressed portions of variable lengths. The compiler system (190) partitions some or all memory lines (115) of the memory (110) into P≧2 partitions, e.g., &agr; and &bgr;, and writes code portions A to a first partition (e.g., &agr;) and second code portions B to a second partition (e.g., &bgr;) of an adjacent memory line (115). The compiler system (190) also stores addresses for some or all of the code portions in, for example, the memory (110). The addresses (260) have pointers (a and b) which indicate start positions (jA and jB) for portions A and B. Optionally, pointer magnitudes distinguish portion-to-pointer relations without the need for further identification bits.

Abstract: A converter (130) comprises a multiplex-buffer (410) at a bus (120), a decoder (420), an output buffer (430) and a comparator (440). The multiplex-buffer (410) forwards VMAX bits (260) of Huffman coded code portions (222) from the bus (120) to the decoder (410). The VMAX bits (260) can comprise further bits set to logical “1” or “0” at random. On a control output (414), the multiplex-buffer (410) provides a signal K identifying which of the VMAX bits are valid or invalid. The decoder (420) maps the VMAX bits (260) into a preliminary bit cluster (426) and indicates a code length V regardless whether some or all bits are valid or not. The comparator (440) checks V and K and allows the output buffer (430) to copy the preliminary bit cluster (426) into instruction portions (212) only when the code length fits the identification of valid bits.