Abstract: Serializer/deserializer (SerDes) modules, equalizers, and equalization techniques having robust parameter initialization may substantially reduce convergence time. One illustrative equalizer includes: a discrete-time, finite impulse response (“FIR”) filter to convert a receive signal to a filtered signal; a decision element to determine channel symbols represented by the filtered signal; and a controller. The controller is configured to, for each of multiple values in a search range, estimate a performance of the equalizer based on the channel symbols and at least one of the filtered signal or an input signal to the decision element; configured to find a centroid value based on the performance for each of the multiple parameter values in the search range; and configured to derive an initial value for the parameter from the centroid value.