Abstract: Generating reports for critical path evaluation and tuning. A predetermined critical path in a circuit design is detected. The predetermined critical path includes a plurality of interconnects between at least two macros. At least one output or at least one input is detected for each of the at least two macros associated with the predetermined critical path. Additionally, a routing description and a buffer location corresponding to the predetermined critical path are detected and a reduced layout design is built. The reduced layout design includes the predetermined critical path and the at least two macros. Furthermore, a timing report is generated based on the reduced layout design, and a circuit based on the circuit design is manufactured in response to detecting the timing report based on the reduced layout design satisfies a predetermined condition.

Abstract: Generating reports for critical path evaluation and tuning. A predetermined critical path in a circuit design is detected. The predetermined critical path includes a plurality of interconnects between at least two macros. At least one output or at least one input is detected for each of the at least two macros associated with the predetermined critical path. Additionally, a routing description and a buffer location corresponding to the predetermined critical path are detected and a reduced layout design is built. The reduced layout design includes the predetermined critical path and the at least two macros. Furthermore, a timing report is generated based on the reduced layout design, and a circuit based on the circuit design is manufactured in response to detecting the timing report based on the reduced layout design satisfies a predetermined condition.

Abstract: A parameterized cell library including variable names corresponding to characteristics of components on an integrated circuit design may reference variable values stored in a first rule layer via internally used rule names stored in a second rule layer. The first and second rule layers may be stored as association tables. The first rule layer may store rule names corresponding to one or more geometric constraints of the integrated circuit design, and the rule names may directly reference variable values derived from a technology manual. The second rule layer may store internally used rule names corresponding to rule names stored in the first rule layer, and the internally used rule names may reference the rule names stored in the first rule layer.

Abstract: Disclosed is a system and method for designing a register layout. According to some embodiments of the present invention, a technology specification is combined with project specifications to produce a set of project specific layout constraints. The project specific constraints may be used to produce a layout.

Abstract: A method is provided for designing an integrated circuit. The method includes inserting wire model objects into the schematic of said circuit based on sizing and placement of components of the circuit, and performing an early timing analysis on said schematic. The steps of inserting and performing are repeated after re-sizing and/or re-placing the components if early timing analysis fails.

Abstract: The present invention is a method and system for modeling wiring routing in circuit design. According to some embodiments, the wire model objects (“WMO”) may be inserted into the wiring routing on a ‘WMO-per-segment’ basis. According to some other embodiments, the wire model objects may be inserted into the wiring routing per groups of sequential segments. The entire wiring routing geometry may constitutes one group, and a wire model object may be inserted between the source point(s) and the target points based on the longest path in the routing geometry. An insertion rule may be selected based on any combination of the following factors: segment length, total path length, spacing between adjacent segments, wire metal and wire width. A wire model object may be selected from a group consisting of: {“C”; one “RC” arrangement; ‘n’ times “?”-type filter arrangement, wherein n=1, 2, 3, . . . , }.

Abstract: The present invention is a method and system for schematically embedding wire model objects into a schematic design of an integrated circuit. The method includes estimating a wiring routing geometry for each signal path in the circuit, selecting one or more cascading wire model objects (“WMOs”) for each segment in each geometry, and substituting each signal path with the respective one or more WMOs.

Abstract: The present invention is a method and system for modeling wiring routing in circuit design. According to some embodiments, the wire model objects (“WMO”) may be inserted into the wiring routing on a ‘WMO-per-segment’ basis. According to some other embodiments, the wire model objects may be inserted into the wiring routing per groups of sequential segments. The entire wiring routing geometry may constitutes one group, and a wire model object may be inserted between the source point(s) and the target points based on the longest path in the routing geometry. An insertion rule may be selected based on any combination of the following factors: segment length, total path length, spacing between adjacent segments, wire metal and wire width. A wire model object may be selected from a group consisting of: {“C”; one “RC” arrangement; ‘n’ times “?”-type filter arrangement, wherein n=1, 2, 3, . . . , }.

Abstract: The present invention is a method and system for schematically embedding wire model objects into a schematic design of an integrated circuit. The method includes estimating a wiring routing geometry for each signal path in the circuit, selecting one or more cascading wire model objects (“WMOs”) for each segment in each geometry, and substituting each signal path with the respective one or more WMOs.

Abstract: A method is provided for designing an integrated circuit. The method includes inserting wire model objects into the schematic of said circuit based on sizing and placement of components of the circuit, and performing an early timing analysis on said schematic. The steps of inserting and performing are repeated after re-sizing and/or re-placing the components if early timing analysis fails.