Patents by Inventor Alex Rubin
Alex Rubin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10169503Abstract: A method, system and computer program product perform timing analysis of an integrated circuit design with callback-based constraint processing for clock domain independence. A timing graph representation of the integrated circuit design includes nodes interconnected by edges. Loading timing abstracts representing the nodes of the timing graph precedes obtaining a timing result based on propagating timing values and associated timing tags from an input to an output of the integrated circuit design and processing timing constraints at one or more of the nodes as callbacks. Each timing tag indicates a clock domain. After applying a design change, one or more modified timing tags that are added or changed as a result of the design change are determined. The timing constraints associated with the modified timing tags are processed as callbacks, and the timing result are re-computed.Type: GrantFiled: February 15, 2018Date of Patent: January 1, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Naiju K. Abdul, Adil Bhanji, Hemlata Gupta, Kerim Kalafala, Alex Rubin, Manish Verma
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Publication number: 20180173833Abstract: A method, system and computer program product perform timing analysis of an integrated circuit design with callback-based constraint processing for clock domain independence. A timing graph representation of the integrated circuit design includes nodes interconnected by edges. Loading timing abstracts representing the nodes of the timing graph precedes obtaining a timing result based on propagating timing values and associated timing tags from an input to an output of the integrated circuit design and processing timing constraints at one or more of the nodes as callbacks. Each timing tag indicates a clock domain. After applying a design change, one or more modified timing tags that are added or changed as a result of the design change are determined. The timing constraints associated with the modified timing tags are processed as callbacks, and the timing result are re-computed.Type: ApplicationFiled: February 15, 2018Publication date: June 21, 2018Inventors: Naiju K. Abdul, Adil Bhanji, Hemlata Gupta, Kerim Kalafala, Alex Rubin, Manish Verma
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Patent number: 9977850Abstract: A method, system and computer program product perform timing analysis of an integrated circuit design with callback-based constraint processing for clock domain independence. A timing graph representation of the integrated circuit design includes nodes interconnected by edges. Loading timing abstracts representing the nodes of the timing graph precedes obtaining a timing result based on propagating timing values and associated timing tags from an input to an output of the integrated circuit design and processing timing constraints at one or more of the nodes as callbacks. Each timing tag indicates a clock domain. After applying a design change, one or more modified timing tags that are added or changed as a result of the design change are determined. The timing constraints associated with the modified timing tags are processed as callbacks, and the timing result are re-computed.Type: GrantFiled: July 12, 2016Date of Patent: May 22, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Naiju K. Abdul, Adil Bhanji, Hemlata Gupta, Kerim Kalafala, Alex Rubin, Manish Verma
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Publication number: 20180018421Abstract: A method, system and computer program product perform timing analysis of an integrated circuit design with callback-based constraint processing for clock domain independence. A timing graph representation of the integrated circuit design includes nodes interconnected by edges. Loading timing abstracts representing the nodes of the timing graph precedes obtaining a timing result based on propagating timing values and associated timing tags from an input to an output of the integrated circuit design and processing timing constraints at one or more of the nodes as callbacks. Each timing tag indicates a clock domain. After applying a design change, one or more modified timing tags that are added or changed as a result of the design change are determined. The timing constraints associated with the modified timing tags are processed as callbacks, and the timing result are re-computed.Type: ApplicationFiled: July 12, 2016Publication date: January 18, 2018Inventors: Naiju K. Abdul, Adil Bhanji, Hemlata Gupta, Kerim Kalafala, Alex Rubin, Manish Verma
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Patent number: 9542524Abstract: Disclosed are a system and a method for performing a timing analysis of an integrated circuit (IC). An internal timing constraint of a logic device in a first signal pathway of a hierarchical entity in an IC design is determined based on a reference value and, if necessary, on library information. A first boundary timing constraint associated with the first signal pathway is derived based on the internal timing constraint and a second boundary timing constraint associated with the first signal pathway is derived based on the first boundary timing constraint and a target slack value for the internal timing constraint. A static timing analysis is performed using the second boundary timing constraint. Based on the analysis, a timing abstraction for the hierarchical entity is generated. A timing model for the IC design is generated using the timing abstraction and other timing abstractions for other hierarchical entities in the design.Type: GrantFiled: January 27, 2015Date of Patent: January 10, 2017Assignee: International Business Machines CorporationInventors: James C. Gregerson, David J. Hathaway, Kerim Kalafala, Tsz-Mei Ko, Alex Rubin
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Publication number: 20160217245Abstract: Disclosed are a system and a method for performing a timing analysis of an integrated circuit (IC). An internal timing constraint of a logic device in a first signal pathway of a hierarchical entity in an IC design is determined based on a reference value and, if necessary, on library information. A first boundary timing constraint associated with the first signal pathway is derived based on the internal timing constraint and a second boundary timing constraint associated with the first signal pathway is derived based on the first boundary timing constraint and a target slack value for the internal timing constraint. A static timing analysis is performed using the second boundary timing constraint. Based on the analysis, a timing abstraction for the hierarchical entity is generated. A timing model for the IC design is generated using the timing abstraction and other timing abstractions for other hierarchical entities in the design.Type: ApplicationFiled: January 27, 2015Publication date: July 28, 2016Inventors: James C. Gregerson, David J. Hathaway, Kerim Kalafala, Tsz-Mei Ko, Alex Rubin
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Patent number: 8795457Abstract: A fabrication method of forming a thermoplastic composite laminate material with tailored and varying thickness in a continuous process. This process utilizes automated equipment or hand lay-up to collate parts or components into a multi-layer stack. Each stack contains all plies, including ply build-up areas, tacked in the proper location to maintain orientation and location. The consolidation tooling contains all necessary part features and is coordinated to the customized multiple ply stacks to form a single integrated thermoplastic composite laminate potentially having areas of differing thickness from these multiple ply stacks.Type: GrantFiled: August 26, 2010Date of Patent: August 5, 2014Assignee: The Boeing CompanyInventors: Alex Rubin, James Fox, Randall Wilkerson
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Patent number: 8776004Abstract: Determining static timing analysis margin on non-controlling inputs of clock shaping and other digital circuits using reverse merge timing includes: selecting one or more circuits within the logic design having a plurality of inputs and using reverse merge; identifying a controlling input of the selected circuit from among this plurality of inputs; and determining for at least one non-controlling input of the circuit, a timing value that may be used to drive design optimization based on the difference between arrival times of the controlling and non-controlling inputs.Type: GrantFiled: January 14, 2011Date of Patent: July 8, 2014Assignee: International Business Machines CorporationInventors: Frank Borkam, Hemlata Gupta, David J. Hathaway, Kerim Kalafala, Vasant Rao, Alex Rubin
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Publication number: 20120185810Abstract: Determining static timing analysis margin on non-controlling inputs of clock shaping and other digital circuits using reverse merge timing includes: selecting one or more circuits within the logic design having a plurality of inputs and using reverse merge; identifying a controlling input of the selected circuit from among this plurality of inputs; and determining for at least one non-controlling input of the circuit, a timing value that may be used to drive design optimization based on the difference between arrival times of the controlling and non-controlling inputs.Type: ApplicationFiled: January 14, 2011Publication date: July 19, 2012Applicant: International Business Machines CorporationInventors: Frank Borkam, Hemlata Gupta, David J. Hathaway, Kerim Kalafala, Vasant Rao, Alex Rubin
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Patent number: 7937604Abstract: A method for generating a skew schedule for a clock distribution network generates a schedule that accounts for both the timing requirements of the memory elements at the endpoints of the clock distribution network and the timing requirements of the gating signals that feed clock gates and other clock control elements within the clock distribution network. The method provides a total solution to the skew scheduling problem by way of a two-phase iterative process. The two phases of the process alternately keep track of the schedule generated by first taking the gating elements of the clock distribution network into account, followed by balancing any remaining skew that may exist on the memory elements of the same clock distribution network. Finally, the method describes a procedure to post-process the skew schedule to ensure that it can be implemented using a clock tree generation tool.Type: GrantFiled: April 19, 2007Date of Patent: May 3, 2011Assignee: International Business Machines CorporationInventors: Revanta Banerji, David J. Hathaway, Alex Rubin, Alexander J. Suess
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Publication number: 20080263488Abstract: A method for generating a skew schedule for a clock distribution network generates a schedule that accounts for both the timing requirements of the memory elements at the endpoints of the clock distribution network and the timing requirements of the gating signals that feed clock gates and other clock control elements within the clock distribution network. The method provides a total solution to the skew scheduling problem by way of a two-phase iterative process. The two phases of the process alternately keep track of the schedule generated by first taking the gating elements of the clock distribution network into account, followed by balancing any remaining skew that may exist on the memory elements of the same clock distribution network. Finally, the method describes a procedure to post-process the skew schedule to ensure that it can be implemented using a clock tree generation tool.Type: ApplicationFiled: April 19, 2007Publication date: October 23, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Revanta Banerji, David J. Hathaway, Alex Rubin, Alexander J. Suess
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Patent number: 6876950Abstract: A system for utilizing a computer to analyze damage to a structure. The system includes a damage disposition program for determining an appropriate repair procedure for repairing the damage to the structure. Additionally, the system includes a processor for executing the damage disposition program. A predefined set of damage class determination rules are utilized by the damage disposition program to determine a damage class.Type: GrantFiled: April 26, 2002Date of Patent: April 5, 2005Assignee: The Boeing CompanyInventors: Thomas C. Beney, Christopher L. Morris, Terry D. Richardson, Alex Rubin
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Publication number: 20030204332Abstract: A system for utilizing a computer to analyze damage to a structure. The system includes a damage disposition program for determining an appropriate repair procedure for repairing the damage to the structure. Additionally, the system includes a processor for executing the damage disposition program. A predefined set of damage class determination rules are utilized by the damage disposition program to determine a damage class.Type: ApplicationFiled: April 26, 2002Publication date: October 30, 2003Inventors: Thomas C. Beney, Christopher L. Morris, Terry D. Richardson, Alex Rubin