Abstract: A disclosed integrated circuit includes first and second clock generation circuits, a stagger circuit, and a plurality of scan chains. The first clock generation circuit receives a first clock signal and generates a first set of clock pulses having a first frequency in response to receipt of a first clock trigger signal and a first enable signal. The second clock generation circuit receives a second clock signal and generates a second set of clock pulses having a second frequency in response to receipt of a second clock trigger signal and a second enable signal. The stagger circuit generates the first and second clock trigger signals from the global trigger signal at different times. The first set of clock pulses are staggered relative to the second set of clock pulses. The plurality of scan chains test functionality of logic circuitry within the IC chip using the first and second set of clock pulses.

Abstract: Embodiments herein describe a methodology for performing non-destructive LBIST when booting an integrated circuit (IC). In one embodiment, when powered on, the IC begins the boot process (e.g., a POST) which is then paused to perform LBIST. However, instead of corrupting or destroying the boot mode state of the IC, the LBIST is non-destructive. That is, after LBIST is performed, the booting process can be resumed in the same state as when LBIST began.

Abstract: A clock monitoring circuit is disclosed. The clock monitoring circuit is configured to receive first and second clock signals generated in respective clock domains. The clock monitoring circuit includes a first counter configured to count clock cycles of the first clock signal for a first period of time delineated by clock cycles of the second clock signal. The first counter outputs a count value indicating the number of counted clock cycles. The clock monitoring circuit also includes a threshold comparator circuit configured to generate an error signal in response to expiration of the first period of time and the first count value output by the first counter falling outside of an expected range.

Abstract: A hardwired core is embedded in an integrated circuit having programmable circuitry. The hardwired core has a microprocessor; a crossbar interconnect coupled to processor local buses of the microprocessor; and a memory controller interface coupled to the crossbar interconnect. The crossbar interconnect provides pipelines for coupling the hardwired core to the programmable circuitry. The microprocessor, the crossbar interconnect, and the memory controller interface are all capable of operating at a first frequency of operation, and the memory controller interface is further capable of being set to operate at a second frequency of operation having an integer ratio with respect to the first frequency of operation. The crossbar interconnect is configured to direct transactions initiated by the microprocessor to the memory controller interface for accessing one or more memory devices coupled to the memory controller interface via a memory controller.

Abstract: A method for address acknowledgement is described. A memory controller interface is embedded as part of an embedded core in a host integrated circuit. Access to the memory controller interface is arbitrated with an arbiter. An accept signal is sent from the memory controller interface to the arbiter to indicate whether the memory controller interface is ready to receive a transaction. Access to the memory controller interface is requested by a master device for passing the transaction to a memory controller via the arbiter. The arbiter is a proxy for the memory controller interface responsive to the accept signal being asserted. An acknowledgement signal is sent from the arbiter as a proxy for the memory controller interface responsive to receipt of the transaction and the accept signal being asserted.

Abstract: An ASIC block embedded in a host IC has a first clock domain with a first frequency of operation that is at least equal to a second frequency of operation of a second clock domain in the host IC but external to the ASIC block. FPGA logic in the second clock domain interfaces with the ASIC block; and a PLL located in the host integrated circuit but external to the ASIC block is coupled to receive a reference clock signal and configured to generate clock signals. Two of the clock signals are respectively sent to the FPGA logic and the ASIC block to make one appear to be produced earlier in time than the other with respect to the ASIC block to compensate for a clock insertion delay and for a clock-to-output time associated with the FPGA logic that at least approximates zero.

Abstract: The various embodiments of the present invention relate to circuit verification. According to one embodiment of the invention, a method of enabling timing verification of a circuit design comprises steps of generating a timing model of a processor core for a static timing analysis tool; coupling timing data related to the processor core to the static timing analysis tool; extracting resistance and capacitance data for interconnect circuits of the circuit design; coupling the resistance and capacitance data for the interconnect circuits to the static timing analysis tool; and verifying the performance of the circuit design using the static timing analysis tool. According to another embodiment of the invention, a system for enabling timing verification of a circuit design is described.