Abstract: Examples described herein relate to a receiver training method. To configure a static gain for at least one static gain amplifier and a target amplitude for a dynamic gain amplifier, a dynamic gain adjustment is disabled and the dynamic gain amplifier is configured to apply a predetermined fixed gain to the static gain amplified signal to generate a test signal. Furthermore, an effective static gain magnitude for at least one static gain amplifier and an effective amplitude for the test signal are determined based on a link performance metric. The static gain is set to the effective static gain magnitude, and a target amplitude for the dynamic gain amplifier is set to the effective amplitude. Then, the dynamic gain adjustment may be enabled to maintain an amplitude of a dynamic gain amplified signal at an output of the dynamic gain amplifier at the target amplitude by varying the dynamic gain.

Abstract: In one embodiment, a method using a computer system determines a length of a rod for use in spine correction surgery. With images of a patient, a segment of the spine requiring correction is identified along with first and second points at the ends of the segment. Then, a first size and a first position of a first circle are determined based on the image such that a portion of the first circle is generally aligned with a curve of the segment. A second circle with a different size and position is similarly determined based on the image. Both the first and second circles pass adjacent to or through the first point and the second point. A length of a portion of the second circle measured between the first and second points is then used to determine a rod length for a post-surgical spinal alignment.

Abstract: Transferring cache line ownership between processors in a shared memory multi-processor computer system. A request for ownership of a cache line is sent from a requesting processor to a memory unit. The memory unit receives the request and determines which one of a plurality of processors other than the requesting processor has ownership of the requested cache line. The memory sends an ownership recall to that processor. In response to the ownership recall, the other processor sends the requested cache line to the requesting processor, which may send a response to the memory unit to confirm receipt of the requested cache line. The other processor may optionally send a response to the memory unit to confirm that the other processor has sent the requested cache line to the requesting processor. A copy of the data for the requested cache line may, under some circumstances, also be sent to the memory unit by the other processor as part of the response.