Abstract: A method of enabling variable latency data transfers in an electronic device, such as an FPGA with an embedded processor, is described. According to one aspect of the invention, a method comprises steps of providing an address for a data transfer between a memory controller and a peripheral device; coupling an address valid signal to the peripheral device; transferring the data between the memory controller and the peripheral device; and receiving a data transfer complete signal at the memory controller. According to another aspect of the invention, an integrated circuit enabling a variable latency data transfer is described. The integrated circuit comprises peripheral device; a memory controller coupled to the peripheral device; an address valid signal coupled from the memory controller to the peripheral device; and a transfer complete signal coupled from the peripheral device to the memory controller.

Abstract: A method of verifying a circuit implementing a data transfer protocol is disclosed. According to one embodiment of the invention, the method comprises steps of providing a block under test that implements a variable latency data transfer protocol; coupling a verification circuit to the block under test; enabling variable latency data transfers to the block under test; and verifying that the block under test is implementing the variable latency data transfer protocol. The method could be implemented to verify the operation of a memory controller of an FPGA, for example. According to another embodiment, a method enabling a multi-stage verification is disclosed. Finally, specific implementations of a verification circuit coupled to an on-chip memory controller of an FPGA are disclosed.

Abstract: A method of verifying a circuit implementing a data transfer protocol is disclosed. According to one embodiment of the invention, the method comprises steps of providing a block under test that implements a variable latency data transfer protocol; coupling a verification circuit to the block under test; enabling variable latency data transfers to the block under test; and verifying that the block under test is implementing the variable latency data transfer protocol. The method could be implemented to verify the operation of a memory controller of an FPGA, for example. According to another embodiment, a method enabling a multi-stage verification is disclosed. Finally, specific implementations of a verification circuit coupled to an on-chip memory controller of an FPGA are disclosed.