Patents by Inventor Alex Seibulescu

Alex Seibulescu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220147502
    Abstract: Described are input output (IO) device configured to perform operations for performing a table lookup with a single wide key larger than a width of a system bus. These operations comprise: receiving the lookup key; performing a plurality of extraction cycles to determine a plurality of key fragments; calculating a final hash value for the lookup key by sequentially calculating, via a hash chain, an interim hash value for each of the key fragments; determine a read access address for a table entry of a logic table based on the final hash value for the lookup key; determine a plurality of read requests based on the read access address; determine a hit on the table entry with the lookup key by issuing each of the read requests to the memory subsystem; and provide the hit on the table entry to the requesting entity or a next processing entity.
    Type: Application
    Filed: November 6, 2020
    Publication date: May 12, 2022
    Inventors: Kit Chiu CHU, Alex SEIBULESCU
  • Patent number: 9817574
    Abstract: According to one aspect, a method includes determining whether at least one memory storage unit in a first stage of a multi-stage array is available for use by a first counter associated with the first stage, and allocating the at least one memory storage unit for use by the first counter when the at least one memory storage unit is available. When the at least one memory storage unit is not available for use by the first counter, the method includes identifying a second counter stored in a first location in the first stage, the first location including a first memory storage unit and a second memory storage unit, and moving the second counter to a second stage of the multi-stage array, storing a pointer to the second stage in the first memory storage unit, and allocating the second memory storage unit to the first counter.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: November 14, 2017
    Assignee: Cisco Technology, Inc.
    Inventors: Sarang Dharmapurikar, Ganlin Wu, Alex Seibulescu, Wanli Wu
  • Publication number: 20170212684
    Abstract: According to one aspect, a method includes determining whether at least one memory storage unit in a first stage of a multi-stage array is available for use by a first counter associated with the first stage, and allocating the at least one memory storage unit for use by the first counter when the at least one memory storage unit is available. When the at least one memory storage unit is not available for use by the first counter, the method includes identifying a second counter stored in a first location in the first stage, the first location including a first memory storage unit and a second memory storage unit, and moving the second counter to a second stage of the multi-stage array, storing a pointer to the second stage in the first memory storage unit, and allocating the second memory storage unit to the first counter.
    Type: Application
    Filed: January 22, 2016
    Publication date: July 27, 2017
    Inventors: Sarang Dharmapurikar, Ganlin Wu, Alex Seibulescu, Wanli Wu