Abstract: This application provides example traffic balancing methods, network devices, and electronic devices, and relates to the field of communications technologies. An example electronic device can create or maintain a first flowpac, and classify a packet that uses a first node as a destination into the first flowpac. When a network balancing parameter meets a preset condition, a second flowpac is created or maintained. A subsequent packet that uses the first node as a destination is classified into the second flowpac, where packets belonging to a same flowpac have a same destination node and a same sending path, and a sending path of a packet in the second flowpac is different from a sending path of a packet in the first flowpac.

Abstract: A method and devices for reducing the delay in end-to-end delivery of network packets may be achieved by having the transmission (TX) side of the device, tag each cell with a unique packet identifier and with a byte offset parameter where the tagging allows the reception (RX) side of the destination device to perform on-the-fly assembly of cells into packets by directly placing them at corresponding host buffer, and the method may be done for multiple packets concurrently, and hence store and forward buffering is not needed in either the source or the destination devices and the lowest possible end-to-end cut-through latency is achieved.

Abstract: The invention relates to a memory aggregation device for storing a set of input data streams and retrieving data to a set of output data streams, the memory aggregation device comprising: a set of first-in first-out (FIFO) memories each comprising an input and an output; an input interconnector configured to interconnect each one of the set of input data streams to each input of the set of FIFO memories according to an input interconnection matrix; an output interconnector configured to interconnect each output of the set of FIFO memories to each one of the set of output data streams according to an output interconnection matrix; an input selector; an output selector; and a memory controller.

Abstract: The disclosure relates to a traffic scheduling device for scheduling a transmission sequence of data packets, stored in a plurality of traffic flow queues, an eligibility state of each of the traffic flow queues for the scheduling is being maintained in a hierarchical scheduling database describing a relationship among the plurality of traffic flow queues. The traffic scheduling device includes: a plurality of interconnected memory cluster units. Each memory cluster unit is associated to a single or more levels of the hierarchical scheduling database and each memory cluster unit is coupled to at least one co-processors. At least one co-processor is software-programmable to implement a scheduling algorithm. The traffic scheduling device also includes an interface to the plurality of traffic flow queues.

Abstract: The disclosure relates to a traffic scheduling device for scheduling a transmission sequence of data packets, stored in a plurality of traffic flow queues, an eligibility state of each of the traffic flow queues for the scheduling is being maintained in a hierarchical scheduling database describing a relationship among the plurality of traffic flow queues. The traffic scheduling device includes: a plurality of interconnected memory cluster units. Each memory cluster unit is associated to a single or more levels of the hierarchical scheduling database and each memory cluster unit is coupled to at least one co-processors. At least one co-processor is software-programmable to implement a scheduling algorithm. The traffic scheduling device also includes an interface to the plurality of traffic flow queues.

Abstract: A method and devices for reducing the delay in end-to-end delivery of network packets may be achieved by having the transmission (TX) side of the device, tag each cell with a unique packet identifier and with a byte offset parameter where the tagging allows the reception (RX) side of the destination device to perform on-the-fly assembly of cells into packets by directly placing them at corresponding host buffer, and the method may be done for multiple packets concurrently, and hence store and forward buffering is not needed in either the source or the destination devices and the lowest possible end-to-end cut-through latency is achieved.

Abstract: The disclosure relates to a traffic scheduling device for scheduling a transmission sequence of data packets, stored in a plurality of traffic flow queues, an eligibility state of each of the traffic flow queues for the scheduling is being maintained in a hierarchical scheduling database describing a relationship among the plurality of traffic flow queues. The traffic scheduling device includes: a plurality of interconnected memory cluster units. Each memory cluster unit is associated to a single or more levels of the hierarchical scheduling database and each memory cluster unit is coupled to at least one co-processors. At least one co-processor is software-programmable to implement a scheduling algorithm. The traffic scheduling device also includes an interface to the plurality of traffic flow queues.

Abstract: The invention relates to a memory aggregation device for storing a set of input data streams and retrieving data to a set of output data streams, the memory aggregation device comprising: a set of first-in first-out (FIFO) memories each comprising an input and an output; an input interconnector configured to interconnect each one of the set of input data streams to each input of the set of FIFO memories according to an input interconnection matrix; an output interconnector configured to interconnect each output of the set of FIFO memories to each one of the set of output data streams according to an output interconnection matrix; an input selector; an output selector; and a memory controller.

Abstract: The invention relates to a scheduling device for receiving a set of requests and providing a set of grants to the set of requests, the scheduling device comprising: a lookup vector prepare unit configured to provide a lookup vector prepared set of requests depending on the set of requests and a selection mask and to provide a set of acknowledgements to the set of requests; and a prefix forest unit coupled to the lookup vector prepare unit, wherein the prefix forest unit is configured to provide the set of grants as a function of the lookup vector prepared set of requests and to provide the selection mask based on the set of grants.

Abstract: An improved system and method for achieving high precision clock recovery, i.e. reconstruction of the clock signal having the same frequency, over a packet switched network. The proposed method utilizes a minimum network delay approach, which overcomes the problems caused by delay variation of the network and filters out network jitter, such as noise jitter and other “singular” anomalies causing latency deviations. Minimum network delay is defined herein as the time delay in which a packet remains in the network under assumption that all transmission queues through which the packet passes are empty. The proposed system and method perform clock recovery by including an improvement in the form of dynamically varying thresholds. Reconstruction of the clock signal is performed in accordance with the minimum network delay estimation based on an adjustable threshold, i.e., the latency change threshold, which increases when the noise threshold increases and decreases when the noise threshold decreases.

Abstract: An improved system and method for achieving high precision clock recovery, i.e. reconstruction of the clock signal having the same frequency, over a packet switched network. The proposed method utilizes a minimum network delay approach, which overcomes the problems caused by delay variation of the network and filters out network jitter, such as noise jitter and other “singular” anomalies causing latency deviations. Minimum network delay is defined herein as the time delay in which a packet remains in the network under assumption that all transmission queues through which the packet passes are empty. The proposed system and method perform clock recovery by including an improvement in the form of dynamically varying thresholds. Reconstruction of the clock signal is performed in accordance with the minimum network delay estimation based on an adjustable threshold, i.e., the latency change threshold, which increases when the noise threshold increases and decreases when the noise threshold decreases.

Abstract: A high-speed system for processing a packet and routing the packet to a packet destination port, the system comprising: (a) a memory block for storing tabulated entries, (b) a parsing subsystem containing at least one microcode machine for parsing the packet, thereby obtaining at least one search key, (c) a searching subsystem containing at least one microcode machine for searching for a match between said at least one search key and said tabulated entries, (d) a resolution subsystem containing at least one microcode machine for resolving the packet destination port, and (e) a modification subsystem containing at least one microcode machine for making requisite modifications to the packet; wherein at least one of said microcode machines is a customized microcode machine.

Abstract: A method for storing and retrieving a key using a hash table, the method comprising the steps of: (a) hashing the key using a first hash function, thereby transforming the key into a table address in the hash table; (b) hashing the key using a second hash function, distinct from the first hash function, thereby transforming the key into a key signature; and (c) entering the key signature in a signature page located at the table address.

Abstract: A system for storing and retrieving data using a radix-search tree having a plurality of sub-trees containing nodes and leaves, the system including: (a) a data storage module designed and configured for storing the plurality of sub-trees, wherein at least one of the leaves contains at least one entry having at least one wildcard in a primary position, and (b) a processor that is operative to perform operations including: (i) building the radix-search tree in the data storage module, and (ii) retrieving data from the radix-search tree in the data storage module.

Abstract: A method and system for storing and retrieving data using a radix-search tree is disclosed. The method encorporates: (a) storing a plurality of nodes, each of the nodes having node-attributes, in a radix-search tree, and (b) retrieving the node-attributes of the plurality of nodes in single memory access. The system encorporates: (a) a data storage module for storing a plurality of sub-trees containing a plurality of nodes having node attributes, wherein the node attributes of at least one of the sub-trees are stored in a contiguous memory block, and (b) a processor that is operative to perform operations including: (i) transferring the node attributes of at least one of the sub-trees to the data storage module, and (ii) retrieving the node attributes of at least one of the sub-tree s from the data storage module.

Abstract: A system for storing and retrieving data using a radix-search tree having a plurality of sub-trees containing nodes and leaves, the system including: (a) a data storage module designed and configured for storing the plurality of sub-trees, wherein at least one of the leaves contains at least one entry having at least one wildcard in a primary position, and (b) a processor that is operative to perform operations including: (i) building the radix-search tree in the data storage module, and (ii) retrieving data from the radix-search tree in the data storage module.