Patents by Inventor Alex Tang
Alex Tang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12189960Abstract: Embodiments include methods, systems, devices, instructions, and media for limiting hot-cold swap wear leveling in memory devices. In one embodiment, wear metric values are stored and monitored using multiple wear leveling criteria. The multiple wear leveling criteria include a hot-cold swap wear leveling criteria, which may make use of a write count offset value. Based on a first wear metric value of a first management group and a second wear metric value of a second management group, the first management group and the second management group are selected for a wear leveling swap operation. The wear leveling swap operation is performed with a whole management group read operation of the first management group to read a set of data, and a whole management group write operation to write the set of data to the second management group.Type: GrantFiled: September 27, 2022Date of Patent: January 7, 2025Assignee: Micron Technology, Inc.Inventors: Fangfang Zhu, Ying Yu Tai, Ning Chen, Jiangli Zhu, Alex Tang
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Patent number: 11789861Abstract: In an embodiment, a system includes a plurality of memory components that each include a plurality of management groups. Each management group includes a plurality of sub-groups. The system also includes a processing device that is operatively coupled with the plurality of memory components to perform wear-leveling operations that include maintaining a sub-group-level delta write count (DWC) for each of the sub-groups of each of the management groups of a memory component in the plurality of memory components. The wear-leveling operations also include determining, in connection with a write operation to a first sub-group of a first management group of the memory component, that a sub-group-level DWC for the first sub-group equals a management-group-move threshold, and responsively triggering a management-group-move operation from the first management group to a second management group of the memory component.Type: GrantFiled: May 12, 2022Date of Patent: October 17, 2023Assignee: Micron Technology, Inc.Inventors: Paul Stonelake, Ning Chen, Fangfang Zhu, Alex Tang
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Fully managed repository to create, version, and share curated data for machine learning development
Patent number: 11704299Abstract: Techniques and technologies for providing a fully managed datastore for clients to securely store, discover, retrieve, remove, and share curated data, or features, to develop machine learning (ML) models in an efficient manner. The feature store service may provide clients with the ability to create and store feature groups that include features and associated metadata providing clients with a quick understanding of features so that they may determine which features are suitable for training ML models and/or use with ML models. The feature store service may provide first a data store configured to store the most recent values associated with a feature group, such that client can access the features and utilize ML models to make real-time predictions with low latency and high throughput, and a second datastore configured to store historical values associated with a feature group, such that a client can utilize the features to train ML models.Type: GrantFiled: March 18, 2021Date of Patent: July 18, 2023Assignee: Amazon Technologies, Inc.Inventors: Tanya Bansal, Vidhi Kastuar, Saurabh Gupta, Alex Tang, Lakshmi Naarayanan Ramakrishnan, Stefano Stefani, Xingyuan Wang, Mukesh Karki -
Patent number: 11681472Abstract: Devices, methods, and media are described for unmap support in coarse mapped storage. In one embodiment a controller of a memory sub-system manages a set of metadata for super management units (SMU) of the memory sub-system, wherein each SMU of the memory sub-system comprises a plurality of data management units (MU), and wherein each MU comprises a plurality of addressable memory elements as part of a coarse memory storage of the memory sub-system. The controller processes a trim command for a first SMU of the plurality of SMUs, and adjusts a trim bit associated with metadata for the first SMU. This trim bit can then be used to manage read and write operations as the trimmed unit waits to be written with an unmap data pattern. Similarly, a trim bit in MU metadata can be used manage related operations to prevent memory access errors.Type: GrantFiled: October 1, 2021Date of Patent: June 20, 2023Assignee: Micron Technology, Inc.Inventors: Fangfang Zhu, Ying Yu Tai, Ning Chen, Jiangli Zhu, Alex Tang
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Publication number: 20230019910Abstract: Embodiments include methods, systems, devices, instructions, and media for limiting hot-cold swap wear leveling in memory devices. In one embodiment, wear metric values are stored and monitored using multiple wear leveling criteria. The multiple wear leveling criteria include a hot-cold swap wear leveling criteria, which may make use of a write count offset value. Based on a first wear metric value of a first management group and a second wear metric value of a second management group, the first management group and the second management group are selected for a wear leveling swap operation. The wear leveling swap operation is performed with a whole management group read operation of the first management group to read a set of data, and a whole management group write operation to write the set of data to the second management group.Type: ApplicationFiled: September 27, 2022Publication date: January 19, 2023Inventors: Fangfang Zhu, Ying Yu Tai, Ning Chen, Jiangli Zhu, Alex Tang
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Patent number: 11481119Abstract: Embodiments include methods, systems, devices, instructions, and media for limiting hot-cold swap wear leveling in memory devices. In one embodiment, wear metric values are stored and monitored using multiple wear leveling criteria. The multiple wear leveling criteria include a hot-cold swap wear leveling criteria, which may make use of a write count offset value. Based on a first wear metric value of a first management group and a second wear metric value of a second management group, the first management group and the second management group are selected for a wear leveling swap operation. The wear leveling swap operation is performed with a whole management group read operation of the first management group to read a set of data, and a whole management group write operation to write the set of data to the second management group.Type: GrantFiled: May 14, 2020Date of Patent: October 25, 2022Assignee: Micron Technology, Inc.Inventors: Fangfang Zhu, Ying Yu Tai, Ning Chen, Jiangli Zhu, Alex Tang
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Publication number: 20220269598Abstract: In an embodiment, a system includes a plurality of memory components that each include a plurality of management groups. Each management group includes a plurality of sub-groups. The system also includes a processing device that is operatively coupled with the plurality of memory components to perform wear-leveling operations that include maintaining a sub-group-level delta write count (DWC) for each of the sub-groups of each of the management groups of a memory component in the plurality of memory components. The wear-leveling operations also include determining, in connection with a write operation to a first sub-group of a first management group of the memory component, that a sub-group-level DWC for the first sub-group equals a management-group-move threshold, and responsively triggering a management-group-move operation from the first management group to a second management group of the memory component.Type: ApplicationFiled: May 12, 2022Publication date: August 25, 2022Inventors: Paul Stonelake, Ning Chen, Fangfang Zhu, Alex Tang
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Patent number: 11360885Abstract: In an embodiment, a system includes a plurality of memory components that each include a plurality of management groups. Each management group includes a plurality of sub-groups. The system also includes a processing device that is operatively coupled with the plurality of memory components to perform wear-leveling operations that include maintaining a sub-group-level delta write count (DWC) for each of the sub-groups of each of the management groups of a memory component in the plurality of memory components. The wear-leveling operations also include determining, in connection with a write operation to a first sub-group of a first management group of the memory component, that a sub-group-level DWC for the first sub-group equals a management-group-move threshold, and responsively triggering a management-group-move operation from the first management group to a second management group of the memory component.Type: GrantFiled: February 21, 2020Date of Patent: June 14, 2022Assignee: Micron Technology, Inc.Inventors: Paul Stonelake, Ning Chen, Fangfang Zhu, Alex Tang
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Publication number: 20220019383Abstract: Devices, methods, and media are described for unmap support in coarse mapped storage. In one embodiment a controller of a memory sub-system manages a set of metadata for super management units (SMU) of the memory sub-system, wherein each SMU of the memory sub-system comprises a plurality of data management units (MU), and wherein each MU comprises a plurality of addressable memory elements as part of a coarse memory storage of the memory sub-system. The controller processes a trim command for a first SMU of the plurality of SMUs, and adjusts a trim bit associated with metadata for the first SMU. This trim bit can then be used to manage read and write operations as the trimmed unit waits to be written with an unmap data pattern. Similarly, a trim bit in MU metadata can be used manage related operations to prevent memory access errors.Type: ApplicationFiled: October 1, 2021Publication date: January 20, 2022Inventors: Fangfang Zhu, Ying Yu Tai, Ning Chen, Jiangli Zhu, Alex Tang
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Patent number: 11216218Abstract: Devices, methods, and media are described for unmap support in coarse mapped storage. In one embodiment a controller of a memory sub-system manages a set of metadata for super management units (SMU) of the memory sub-system, wherein each SMU of the memory sub-system comprises a plurality of data management units (MU), and wherein each MU comprises a plurality of addressable memory elements as part of a coarse memory storage of the memory sub-system. The controller processes a trim command for a first SMU of the plurality of SMUs, and adjusts a trim bit associated with metadata for the first SMU. This trim bit can then be used to manage read and write operations as the trimmed unit waits to be written with an unmap data pattern. Similarly, a trim bit in MU metadata can be used manage related operations to prevent memory access errors.Type: GrantFiled: April 22, 2020Date of Patent: January 4, 2022Assignee: Micron Technology, Inc.Inventors: Fangfang Zhu, Ying Yu Tai, Ning Chen, Jiangli Zhu, Alex Tang
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Patent number: 11042316Abstract: A device may include a SSD having multiple storage units and a deduplication control circuit configured to determine whether selected data content to be stored is a duplicate of previous data content already in a first buffer of data buffered to be stored in a set of storage units. The deduplication circuit may be further configured to, based on a determination that the selected data content is a duplicate of first previous data content already buffered in the first buffer, instead of buffering another copy of the selected data content, buffer a first header including a first pointer that associates the first header with the first previous data content already buffered in the first buffer. The deduplication circuit may also be configured to reorder the first buffer such that individual data contents in the first buffer are grouped near headers associated with the individual data contents.Type: GrantFiled: September 9, 2019Date of Patent: June 22, 2021Assignee: seagate technology llcInventors: Hongmei Xie, AbdelHakim Alhussien, Sundararajan Sankaranarayanan, Alex Tang, Leonid Baryudin, Erich Franz Haratsch
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Publication number: 20210019058Abstract: Embodiments include methods, systems, devices, instructions, and media for limiting hot-cold swap wear leveling in memory devices. In one embodiment, wear metric values are stored and monitored using multiple wear leveling criteria. The multiple wear leveling criteria include a hot-cold swap wear leveling criteria, which may make use of a write count offset value. Based on a first wear metric value of a first management group and a second wear metric value of a second management group, the first management group and the second management group are selected for a wear leveling swap operation. The wear leveling swap operation is performed with a whole management group read operation of the first management group to read a set of data, and a whole management group write operation to write the set of data to the second management group.Type: ApplicationFiled: May 14, 2020Publication date: January 21, 2021Inventors: Fangfang Zhu, Ying Yu Tai, Ning Chen, Jiangli Zhu, Alex Tang
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Publication number: 20210019254Abstract: In an embodiment, a system includes a plurality of memory components that each include a plurality of management groups. Each management group includes a plurality of sub-groups. The system also includes a processing device that is operatively coupled with the plurality of memory components to perform wear-leveling operations that include maintaining a sub-group-level delta write count (DWC) for each of the sub-groups of each of the management groups of a memory component in the plurality of memory components. The wear-leveling operations also include determining, in connection with a write operation to a first sub-group of a first management group of the memory component, that a sub-group-level DWC for the first sub-group equals a management-group-move threshold, and responsively triggering a management-group-move operation from the first management group to a second management group of the memory component.Type: ApplicationFiled: February 21, 2020Publication date: January 21, 2021Inventors: Paul Stonelake, Ning Chen, Fangfang Zhu, Alex Tang
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Publication number: 20210019088Abstract: Devices, methods, and media are described for unmap support in coarse mapped storage. In one embodiment a controller of a memory sub-system manages a set of metadata for super management units (SMU) of the memory sub-system, wherein each SMU of the memory sub-system comprises a plurality of data management units (MU), and wherein each MU comprises a plurality of addressable memory elements as part of a coarse memory storage of the memory sub-system. The controller processes a trim command for a first SMU of the plurality of SMUs, and adjusts a trim bit associated with metadata for the first SMU. This trim bit can then be used to manage read and write operations as the trimmed unit waits to be written with an unmap data pattern. Similarly, a trim bit in MU metadata can be used manage related operations to prevent memory access errors.Type: ApplicationFiled: April 22, 2020Publication date: January 21, 2021Inventors: Fangfang Zhu, Ying Yu Tai, Ning Chen, Jiangli Zhu, Alex Tang
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Patent number: 10740251Abstract: The implementations described herein provide a hybrid drive with a storage capacity including solid-state drive (NAND) technology and hard disc drive (HDD) technology. A translation layer is stored in the solid-state drive and includes plurality of entries. Each entry of the plurality of entries corresponds to at least one logical data unit and includes a cache state indicating where the data corresponding to the logical data unit is located and whether the data is valid. The translation layer may be a multi-layer map that includes a sparse mapping scheme. In a sparse multi-layer map, entries are leaf entries or non-leaf entries. Leaf entries include a cache state for the corresponding logical data unit(s). Non-leaf entries may include a pointer to a lower level mapping for a plurality of logical data units.Type: GrantFiled: January 20, 2017Date of Patent: August 11, 2020Assignee: SEAGATE TECHNOLOGY LLCInventors: Alex Tang, Leonid Baryudin, Timothy Canepa, Jackson Ellis
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Patent number: 10635581Abstract: A garbage collection method comprises selecting one or blocks in a SSD of a hybrid drive for garbage collection; determining a state of data of the one or more selected blocks, wherein the state suggests a location and temperature of data; and executing a garbage collection efficiency and caching efficiency action on the data of the one or more selected blocks based on the determined state. The garbage collection process may utilize the state information provided by the cache layer of the hybrid drive to make decisions regarding data in the one or more selected blocks.Type: GrantFiled: January 20, 2017Date of Patent: April 28, 2020Assignee: SEAGATE TECHNOLOGY LLCInventors: Alex Tang, Leonid Baryudin, Timothy Canepa, Mark Ish, Jackson Ellis
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Patent number: 10409518Abstract: A device may include a SSD having multiple storage units and a deduplication control circuit configured to determine whether selected data content to be stored is a duplicate of previous data content already in a first buffer of data buffered to be stored in a set of storage units. The deduplication circuit may be further configured to, based on a determination that the selected data content is a duplicate of first previous data content already buffered in the first buffer, instead of buffering another copy of the selected data content, buffer a first header including a first pointer that associates the first header with the first previous data content already buffered in the first buffer. The deduplication circuit may also be configured to reorder the first buffer such that individual data contents in the first buffer are grouped near headers associated with the individual data contents.Type: GrantFiled: April 20, 2017Date of Patent: September 10, 2019Assignee: Seagate Technology LLCInventors: Hongmei Xie, AbdelHakim Alhussien, Sundararajan Sankaranarayanan, Alex Tang, Leonid Baryudin, Erich Franz Haratsch
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Patent number: 10394493Abstract: Apparatus and method for managing data in a hybrid data storage device. The device has a first non-volatile memory (NVM) of solid state memory cells arranged into a first set of garbage collection units (GCUs), and a second NVM as a rotatable data recording medium arranged into a second set of GCUs each comprising a plurality of shingled magnetic recording tracks. A control circuit combines a first group of logical block units (LBUs) stored in the first set of GCUs with a second group of LBUs stored in the second set of GCUs to form a combined group of LBUs arranged in sequential order by logical address. The control circuit streams the combined group of LBUs to a zone of shingled magnetic recording tracks in a selected one of the second set of GCUs. A combined media translation map identifies physical addresses in both the first and second NVMs.Type: GrantFiled: June 30, 2017Date of Patent: August 27, 2019Assignee: Seagate Technology LLCInventors: Alex Tang, Leonid Baryudin, Michael Scott Hicken, Mark Ish, Carl Forhan
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Patent number: 10268404Abstract: Systems and methods presented herein provide for open block handling of an SSD. In one embodiment, an SSD includes a buffer, and an MLC flash device. The SSD also includes a controller operable to write data in the buffer based on an Input/Output (I/O) request (e.g., from a host), to begin copying the data from the buffer to a block of the MLC flash device, to copy a portion of the data associated with open word lines of the block to another location in the buffer after a power cycle, and to update a lookup table for the copied portion of the data with the other location so that the copied portion of the data can be accessed via a subsequent I/O request.Type: GrantFiled: March 28, 2018Date of Patent: April 23, 2019Assignee: Seagate Technology LLCInventors: Abdel Hakim Alhussien, Alex Tang, Leonid Baryudin, Erich Franz Haratsch
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Publication number: 20190004739Abstract: Apparatus and method for managing data in a hybrid data storage device. The device has a first non-volatile memory (NVM) of solid state memory cells arranged into a first set of garbage collection units (GCUs), and a second NVM as a rotatable data recording medium arranged into a second set of GCUs each comprising a plurality of shingled magnetic recording tracks. A control circuit combines a first group of logical block units (LBUs) stored in the first set of GCUs with a second group of LBUs stored in the second set of GCUs to form a combined group of LBUs arranged in sequential order by logical address. The control circuit streams the combined group of LBUs to a zone of shingled magnetic recording tracks in a selected one of the second set of GCUs. A combined media translation map identifies physical addresses in both the first and second NVMs.Type: ApplicationFiled: June 30, 2017Publication date: January 3, 2019Inventors: Alex Tang, Leonid Baryudin, Michael Scott Hicken, Mark Ish, Carl Forhan