Patents by Inventor Alex Usenko

Alex Usenko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12211686
    Abstract: Methods of forming SOI substrates are disclosed. In some embodiments, an epitaxial layer and an oxide layer are formed on a sacrificial substrate. An etch stop layer is formed in the epitaxial layer. The sacrificial substrate is bonded to a handle substrate at the oxide layer. The sacrificial substrate is removed. The epitaxial layer is partially removed until the etch stop layer is exposed.
    Type: Grant
    Filed: July 21, 2023
    Date of Patent: January 28, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Alex Usenko
  • Publication number: 20240355937
    Abstract: A method of producing a four-layer silicon diode, including selecting a first silicon wafer, wherein said first silicon wafer is CZ-grown B-doped with <100> orientation, a resistivity of less than 0.01 Ohm-cm, and an oxygen content of greater than 10 ppma, and then selecting a second silicon wafer, wherein said second silicon wafer is CZ-grown P-doped with <100> orientation, a resistivity of less than 0.005 Ohm-cm, and an oxygen content of greater than 10 ppma, followed by cleaning the respective first and second silicon wafers. The wafers are then HF treated to yield respective first and second cleaned wafers, the first cleaned wafer is positioned into a first furnace and the second cleaned wafer is positioned into a second furnace, wherein the first and second furnaces are not unitary.
    Type: Application
    Filed: April 22, 2024
    Publication date: October 24, 2024
    Inventors: Alex Usenko, Anthony Caruso, Steven Bellinger
  • Patent number: 12002891
    Abstract: A method of producing a four-layer silicon diode, including selecting a first silicon wafer, wherein said first silicon wafer is CZ-grown B-doped with <100> orientation, a resistivity of less than 0.01 Ohm-cm, and an oxygen content of greater than 10 ppma, and then selecting a second silicon wafer, wherein said second silicon wafer is CZ-grown P-doped with <100> orientation, a resistivity of less than 0.005 Ohm-cm, and an oxygen content of greater than 10 ppma, followed by cleaning the respective first and second silicon wafers. The wafers are then HF treated to yield respective first and second cleaned wafers, the first cleaned wafer is positioned into a first furnace and the second cleaned wafer is positioned into a second furnace, wherein the first and second furnaces are not unitary.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: June 4, 2024
    Assignee: THE CURATORS OF THE UNIVERSITY OF MISSOURI
    Inventors: Alex Usenko, Anthony Caruso, Steven Bellinger
  • Publication number: 20230369038
    Abstract: Methods of forming SOI substrates are disclosed. In some embodiments, an epitaxial layer and an oxide layer are formed on a sacrificial substrate. An etch stop layer is formed in the epitaxial layer. The sacrificial substrate is bonded to a handle substrate at the oxide layer. The sacrificial substrate is removed. The epitaxial layer is partially removed until the etch stop layer is exposed.
    Type: Application
    Filed: July 21, 2023
    Publication date: November 16, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Alex Usenko
  • Publication number: 20230299210
    Abstract: A method of producing a four-layer silicon diode, including selecting a first silicon wafer, wherein said first silicon wafer is CZ-grown B-doped with <100> orientation, a resistivity of less than 0.01 Ohm-cm, and an oxygen content of greater than 10 ppma, and then selecting a second silicon wafer, wherein said second silicon wafer is CZ-grown P-doped with <100> orientation, a resistivity of less than 0.005 Ohm-cm, and an oxygen content of greater than 10 ppma, followed by cleaning the respective first and second silicon wafers. The wafers are then HF treated to yield respective first and second cleaned wafers, the first cleaned wafer is positioned into a first furnace and the second cleaned wafer is positioned into a second furnace, wherein the first and second furnaces are not unitary.
    Type: Application
    Filed: June 30, 2022
    Publication date: September 21, 2023
    Inventors: Alex Usenko, Anthony Caruso, Steven Bellinger
  • Patent number: 11764054
    Abstract: Methods of forming SOI substrates are disclosed. In some embodiments, an epitaxial layer and an oxide layer are formed on a sacrificial substrate. An etch stop layer is formed in the epitaxial layer. The sacrificial substrate is bonded to a handle substrate at the oxide layer. The sacrificial substrate is removed. The epitaxial layer is partially removed until the etch stop layer is exposed.
    Type: Grant
    Filed: November 15, 2020
    Date of Patent: September 19, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Alex Usenko
  • Patent number: 11699615
    Abstract: A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, an optionally relaxed semiconductor layer comprising silicon, germanium, or silicon germanium, an optional polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: July 11, 2023
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Igor Peidous, Lu Fei, Jeffrey L. Libbert, Andrew M. Jones, Alex Usenko, Gang Wang, Shawn George Thomas, Srikanth Kommu
  • Publication number: 20210384070
    Abstract: A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, an optionally relaxed semiconductor layer comprising silicon, germanium, or silicon germanium, an optional polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer.
    Type: Application
    Filed: August 25, 2021
    Publication date: December 9, 2021
    Inventors: Igor Peidous, Lu Fei, Jeffrey L. Libbert, Andrew M. Jones, Alex Usenko, Gang Wang, Shawn George Thomas, Srikanth Kommu
  • Patent number: 11139198
    Abstract: A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, an optionally relaxed semiconductor layer comprising silicon, germanium, or silicon germanium, an optional polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: October 5, 2021
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Igor Peidous, Lu Fei, Jeffrey L. Libbert, Andrew M. Jones, Alex Usenko, Gang Wang, Shawn George Thomas, Srikanth Kommu
  • Publication number: 20210090876
    Abstract: Methods of forming SOI substrates are disclosed. In some embodiments, an epitaxial layer and an oxide layer are formed on a sacrificial substrate. An etch stop layer is formed in the epitaxial layer. The sacrificial substrate is bonded to a handle substrate at the oxide layer. The sacrificial substrate is removed. The epitaxial layer is partially removed until the etch stop layer is exposed.
    Type: Application
    Filed: November 15, 2020
    Publication date: March 25, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Alex Usenko
  • Patent number: 10923503
    Abstract: Various embodiments of the present application are directed towards a method for forming a semiconductor-on-insulator (SOI) substrate comprising a trap-rich layer with small grain sizes, as well as the resulting SOI substrate. In some embodiments, an amorphous silicon layer is deposited on a high-resistivity substrate. A rapid thermal anneal (RTA) is performed to crystallize the amorphous silicon layer into a trap-rich layer of polysilicon in which a majority of grains are equiaxed. An insulating layer is formed over the trap-rich layer. A device layer is formed over the insulating layer and comprises a semiconductor material. Equiaxed grains are smaller than other grains (e.g., columnar grains). Since a majority of grains in the trap-rich layer are equiaxed, the trap-rich layer has a high grain boundary area and a high density of carrier traps. The high density of carrier traps may, for example, reduce the effects of parasitic surface conduction (PSC).
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: February 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hung Cheng, Cheng-Ta Wu, Yeur-Luen Tu, Min-Ying Tsai, Alex Usenko
  • Patent number: 10840080
    Abstract: Methods of forming SOI substrates are disclosed. In some embodiments, an epitaxial layer and an oxide layer are formed on a sacrificial substrate. An etch stop layer is formed in the epitaxial layer. The sacrificial substrate is bonded to a handle substrate at the oxide layer. The sacrificial substrate is removed. The epitaxial layer is partially removed until the etch stop layer is exposed.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: November 17, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Alex Usenko
  • Publication number: 20200006385
    Abstract: Various embodiments of the present application are directed towards a method for forming a semiconductor-on-insulator (SOI) substrate comprising a trap-rich layer with small grain sizes, as well as the resulting SOI substrate. In some embodiments, an amorphous silicon layer is deposited on a high-resistivity substrate. A rapid thermal anneal (RTA) is performed to crystallize the amorphous silicon layer into a trap-rich layer of polysilicon in which a majority of grains are equiaxed. An insulating layer is formed over the trap-rich layer. A device layer is formed over the insulating layer and comprises a semiconductor material. Equiaxed grains are smaller than other grains (e.g., columnar grains). Since a majority of grains in the trap-rich layer are equiaxed, the trap-rich layer has a high grain boundary area and a high density of carrier traps. The high density of carrier traps may, for example, reduce the effects of parasitic surface conduction (PSC).
    Type: Application
    Filed: July 2, 2018
    Publication date: January 2, 2020
    Inventors: Yu-Hung Cheng, Cheng-Ta Wu, Yeur-Luen Tu, Min-Ying Tsai, Alex Usenko
  • Patent number: 10483152
    Abstract: A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, an optionally relaxed semiconductor layer comprising silicon, germanium, or silicon germanium, an optional polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: November 19, 2019
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Igor Peidous, Lu Fei, Jeffrey L. Libbert, Andrew M. Jones, Alex Usenko, Gang Wang, Shawn George Thomas, Srikanth Kommu
  • Patent number: 10475694
    Abstract: A method is provided for preparing a high resistivity silicon handle substrate for use in semiconductor-on-insulator structure. The handle substrate is prepared to comprise thermally stable charge carrier traps in the region of the substrate that will be at or near the buried oxide layer (BOX) of the final semiconductor-on-insulator structure. The handle substrate comprising the stable carrier traps is manufactured by hydrogen ions implantation occurring using at least two different energies, followed by a 2-step thermal treatment. The thermally stable defect structures prepared thereby is stable to anneal at temperatures of at least 1180° C. The defect structure comprises 3-dimensional network of nano-cavities interconnected by dislocations. This wafer can be used as a handle wafer for fabricating silicon-on-insulator (SOI) wafers and further fabricating radio frequency (RF) semiconductor devices.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: November 12, 2019
    Assignee: GlobalWafers Co., Ltd.
    Inventor: Alex Usenko
  • Patent number: 10290533
    Abstract: A single crystal semiconductor handle substrate for use in the manufacture of semiconductor-on-insulator (e.g., silicon-on-insulator (SOI)) structure is etched to form a porous layer in the front surface region of the wafer. The etched region is oxidized and then filled with a semiconductor material, which may be polycrystalline or amorphous. The surface is polished to render it bondable to a semiconductor donor substrate. Layer transfer is performed over the polished surface thus creating semiconductor-on-insulator (e.g., silicon-on-insulator (SOI)) structure having 4 layers: the handle substrate, the composite layer comprising filled pores, a dielectric layer (e.g., buried oxide), and a device layer. The structure can be used as initial substrate in fabricating radiofrequency chips. The resulting chips have suppressed parasitic effects, particularly, no induced conductive channel below the buried oxide.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: May 14, 2019
    Assignee: GlobalWafers Co., Ltd.
    Inventor: Alex Usenko
  • Publication number: 20190139818
    Abstract: A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, an optionally relaxed semiconductor layer comprising silicon, germanium, or silicon germanium, an optional polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer.
    Type: Application
    Filed: December 28, 2018
    Publication date: May 9, 2019
    Inventors: Igor Peidous, Lu Fei, Jeffrey L. Libbert, Andrew M. Jones, Alex Usenko, Gang Wang, Shawn George Thomas, Srikanth Kommu
  • Publication number: 20190088466
    Abstract: Methods of forming SOI substrates are disclosed. In some embodiments, an epitaxial layer and an oxide layer are formed on a sacrificial substrate. An etch stop layer is formed in the epitaxial layer. The sacrificial substrate is bonded to a handle substrate at the oxide layer. The sacrificial substrate is removed. The epitaxial layer is partially removed until the etch stop layer is exposed.
    Type: Application
    Filed: January 3, 2018
    Publication date: March 21, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Alex Usenko
  • Publication number: 20180138080
    Abstract: A method is provided for preparing a high resistivity silicon handle substrate for use in semiconductor-on-insulator structure. The handle substrate is prepared to comprise thermally stable charge carrier traps in the region of the substrate that will be at or near the buried oxide layer (BOX) of the final semiconductor-on-insulator structure. The handle substrate comprising the stable carrier traps is manufactured by hydrogen ions implantation occurring using at least two different energies, followed by a 2-step thermal treatment. The thermally stable defect structures prepared thereby is stable to anneal at temperatures of at least 1180° C. The defect structure comprises 3-dimensional network of nano-cavities interconnected by dislocations. This wafer can be used as a handle wafer for fabricating silicon-on-insulator (SOI) wafers and further fabricating radio frequency (RF) semiconductor devices.
    Type: Application
    Filed: December 21, 2017
    Publication date: May 17, 2018
    Inventor: Alex Usenko
  • Publication number: 20180047614
    Abstract: A single crystal semiconductor handle substrate for use in the manufacture of semiconductor-on-insulator (e.g., silicon-on-insulator (SOI)) structure is etched to form a porous layer in the front surface region of the wafer. The etched region is oxidized and then filled with a semiconductor material, which may be polycrystalline or amorphous. The surface is polished to render it bondable to a semiconductor donor substrate. Layer transfer is performed over the polished surface thus creating semiconductor-on-insulator (e.g., silicon-on-insulator (SOI)) structure having 4 layers: the handle substrate, the composite layer comprising filled pores, a dielectric layer (e.g., buried oxide), and a device layer. The structure can be used as initial substrate in fabricating radiofrequency chips. The resulting chips have suppressed parasitic effects, particularly, no induced conductive channel below the buried oxide.
    Type: Application
    Filed: March 11, 2016
    Publication date: February 15, 2018
    Inventor: Alex Usenko