Patents by Inventor Alexander Andreopoulos
Alexander Andreopoulos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11556767Abstract: High dynamic range, high class count, high input rate winner-take-all on neuromorphic hardware is provided. In some embodiments, a plurality of thermometer codes are received by a neurosynaptic core. The plurality of thermometer codes are split into a plurality of intervals. One of the plurality of intervals is selected. A local maximum is determined within the one of the plurality of intervals. A global maximum is determined based on the local maximum.Type: GrantFiled: April 7, 2020Date of Patent: January 17, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alexander Andreopoulos, Steven K. Esser, Jeffrey A. Kusnitz
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Patent number: 11537855Abstract: Low spike count ring buffer mechanisms on neuromorphic hardware are provided. A ring buffer comprises a plurality of memory cells. The plurality of memory cells comprises one or more neurosynaptic core. A demultiplexer is operatively coupled to the ring buffer. The demultiplexer is adapted to receive input comprising a plurality of spikes, and write sequentially to each of the plurality of memory cells. A plurality of output connectors is operatively coupled to the ring buffer. Each of the plurality of output connectors is adapted to provide an output based on contents of a subset of the plurality of memory cells.Type: GrantFiled: September 24, 2018Date of Patent: December 27, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Alexander Andreopoulos
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Patent number: 11514298Abstract: High-framerate real-time spatiotemporal disparity mechanisms on neuromorphic hardware are provided. In various embodiments, a first and second spiking input sensor each output a time series of spikes corresponding to a plurality of frames. A neurosynaptic network is configured to receive the time series of spikes corresponding to the plurality of frames; accumulate the time series of spikes in a ring buffer, thereby creating a plurality of temporal scales; for each corresponding pair of frames from the first and second spiking input sensors, determining a mapping of pixels in one of the pair of frames to pixels in the other of the pair of frames based on similarity; based on the pixel mapping, determining a disparity map.Type: GrantFiled: October 31, 2018Date of Patent: November 29, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alexander Andreopoulos, Hirak Jyoti Kashyap, Myron D. Flickner
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Patent number: 11361214Abstract: Dynamic multiscale routing on networks of neurosynaptic cores with a feedback attention beam and short term memory with inhibition of return is provided. In various embodiments, an input topographic map is received at a spiking neuromorphic hardware system. A saliency map is received, associating a saliency value with each of a plurality of regions of the input topographic map. Based on the saliency map, a first of the plurality of regions in order of saliency value is routed. The first of the plurality of regions is suppressed. Based on the saliency map, a predetermined number of the plurality of regions are sequentially routed in order of saliency value.Type: GrantFiled: January 13, 2017Date of Patent: June 14, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Alexander Andreopoulos
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Publication number: 20220164970Abstract: High-framerate real-time spatiotemporal disparity mechanisms on neuromorphic hardware are provided. In various embodiments, a first and second spiking input sensor each output a time series of spikes corresponding to a plurality of frames. A neurosynaptic network is configured to receive the time series of spikes corresponding to the plurality of frames; accumulate the time series of spikes in a ring buffer, thereby creating a plurality of temporal scales; for each corresponding pair of frames from the first and second spiking input sensors, determining a mapping of pixels in one of the pair of frames to pixels in the other of the pair of frames based on similarity; based on the pixel mapping, determining a disparity map.Type: ApplicationFiled: October 31, 2018Publication date: May 26, 2022Inventors: Alexander Andreopoulos, Hirak Jyoti Kashyap, Myron D. Flickner
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Publication number: 20220129436Abstract: Systems are provided that can produce symbolic and numeric representations of the neural network outputs, such that these outputs can be used to validate correctness of the implementation of the neural network. In various embodiments, a description of an artificial neural network containing no data-dependent branching is read. Based on the description of the artificial neural network, a symbolic representation is constructed of an output of the artificial neural network, the symbolic representation comprising at least one variable. The symbolic representation is compared to a ground truth symbolic representation, thereby validating the neural network system.Type: ApplicationFiled: October 22, 2020Publication date: April 28, 2022Inventors: Alexander Andreopoulos, Dharmendra S. Modha, Andrew Stephen Cassidy, Brian Seisho Taba, Carmelo Di Nolfo, Hartmut Penner, John Vernon Arthur, Jun Sawada, Myron D. Flickner, Pallab Datta, Rathinakumar Appuswamy
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Publication number: 20220129742Abstract: Simulation and validation of neural network systems is provided. In various embodiments, a description of an artificial neural network is read. A directed graph is constructed comprising a plurality of edges and a plurality of nodes, each of the plurality of edges corresponding to a queue and each of the plurality of nodes corresponding to a computing function of the neural network system. A graph state is updated over a plurality of time steps according to the description of the neural network, the graph state being defined by the contents of each of the plurality of queues. Each of a plurality of assertions is tested at each of the plurality of time steps, each of the plurality of assertions being a function of a subset of the graph state. Invalidity of the neural network system is indicated for each violation of one of the plurality of assertions.Type: ApplicationFiled: October 22, 2020Publication date: April 28, 2022Inventors: Alexander Andreopoulos, Dharmendra S. Modha, Carmelo Di Nolfo, Myron D. Flickner, Andrew Stephen Cassidy, Brian Seisho Taba, Pallab Datta, Rathinakumar Appuswamy, Jun Sawada
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Patent number: 11227180Abstract: Embodiments of the invention provide a computer-readable medium of visual saliency estimation comprising receiving an input video of image frames. Each image frame has one or more channels, and each channel has one or more pixels. The computer-readable medium further comprises, for each channel of each image frame, generating corresponding neural spiking data based on a pixel intensity of each pixel of the channel, generating a corresponding multi-scale data structure based on the corresponding neural spiking data, and extracting a corresponding map of features from the corresponding multi-scale data structure. The multi-scale data structure comprises one or more data layers, wherein each data layer represents a spike representation of pixel intensities of a channel at a corresponding scale. The computer-readable medium further comprises encoding each map of features extracted as neural spikes.Type: GrantFiled: October 15, 2019Date of Patent: January 18, 2022Assignee: International Business Machines CorporationInventors: Alexander Andreopoulos, Steven K. Esser, Dharmendra S. Modha
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Patent number: 11120561Abstract: Detection, tracking and recognition on networks of digital neurosynaptic cores are provided. In various embodiments, an image sensor is configured to provide a time-series of frames. A first artificial neural network is operatively coupled to the image sensor and configured to detect a plurality of objects in the time-series of frames. A second artificial neural network is operatively coupled to the first artificial neural network and configured to classify objects detected by the first neural network and output a location and classification of said classified objects. The first and second artificial neural networks comprise one or more spike-based neurosynaptic cores.Type: GrantFiled: October 31, 2018Date of Patent: September 14, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alexander Andreopoulos, Arnon Amir, Tapan K. Nayak
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Patent number: 11049000Abstract: Distributed state via cascades of tensor decompositions and neuron activation binding on neuromorphic hardware is provided. In various embodiments, a kernel is divided into a plurality of subkernels. Each subkernel has less than a predetermined size. The plurality of subkernels are distributed, each to one of a plurality of neurosynaptic processors. By each of the plurality of neurosynaptic processors, one of the subkernels is applied to an input to generate a partial convolution. The partial convolutions from each of the plurality of neurosynaptic processors are combined to determine an activation.Type: GrantFiled: March 27, 2018Date of Patent: June 29, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alexander Andreopoulos, Myron D. Flickner
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Patent number: 10970622Abstract: Dynamic gating for neuromorphic systems and the configuration thereof are provided. In various embodiments, neurosynaptic system comprises a neurosynaptic core. The neuromorphic core comprises a plurality of neurons and axons. The neurosynaptic core comprises a programmable gate operative to receive a control signal and selectively output a first output signal based on the control signal. In various embodiments, a plurality of input parameters are read, defining the behavior of a programmable gate. Based upon the plurality of input parameters, a neurosynaptic core is configured to provide a programmable gate operative to receive a control signal and selectively output a first output signal based on the control signal.Type: GrantFiled: January 13, 2017Date of Patent: April 6, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Alexander Andreopoulos
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Patent number: 10846567Abstract: Embodiments of the invention provide a method for scene understanding based on a sequence of image frames. The method comprises converting each pixel of each image frame to neural spikes, and extracting features from the sequence of image frames by processing neural spikes corresponding to pixels of the sequence of image frames. The method further comprises encoding the extracted features as neural spikes, and classifying the extracted features.Type: GrantFiled: October 3, 2019Date of Patent: November 24, 2020Assignee: International Business Machines CorporationInventors: Alexander Andreopoulos, Rathinakumar Appuswamy, Pallab Datta, Steven K. Esser, Dharmendra S. Modha
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Patent number: 10733500Abstract: In one embodiment, a system includes one or more electronic neurons and one or more electronic axons. Each neuron is connected to at least one electronic axon via an electronic synapse, and at least one of the one or more electronic neurons is configured to store information in a membrane potential thereof and/or at least one of the one or more electronic axons is configured to store information in an axon delay buffer thereof to act as a memory. In another embodiment, a computer-implemented method includes storing information to a memory comprising electronic neurons and electronic axons. Information is stored in either a membrane potential of at least one of the electronic neurons or in an axon delay buffer of at least one of the electronic axons. Also, each neuron is connected to at least one electronic axon via an electronic synapse.Type: GrantFiled: October 21, 2015Date of Patent: August 4, 2020Assignee: International Business Machines CorporationInventors: Alexander Andreopoulos, Andrew S. Cassidy
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Publication number: 20200242457Abstract: High dynamic range, high class count, high input rate winner-take-all on neuromorphic hardware is provided. In some embodiments, a plurality of thermometer codes are received by a neurosynaptic core. The plurality of thermometer codes are split into a plurality of intervals. One of the plurality of intervals is selected. A local maximum is determined within the one of the plurality of intervals. A global maximum is determined based on the local maximum.Type: ApplicationFiled: April 7, 2020Publication date: July 30, 2020Inventors: Alexander Andreopoulos, Steven K. Esser, Jeffrey A. Kusnitz
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Patent number: 10650309Abstract: High dynamic range, high class count, high input rate winner-take-all on neuromorphic hardware is provided. In some embodiments, a plurality of thermometer codes are received by a neurosynaptic core. The plurality of thermometer codes are split into a plurality of intervals. One of the plurality of intervals is selected. A local maximum is determined within the one of the plurality of intervals. A global maximum is determined based on the local maximum.Type: GrantFiled: August 9, 2016Date of Patent: May 12, 2020Assignee: INTERNATIONAL MACHINES CORPORATIONInventors: Alexander Andreopoulos, Steven K. Esser, Jeffrey A. Kusnitz
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Publication number: 20200134843Abstract: Detection, tracking and recognition on networks of digital neurosynaptic cores are provided. In various embodiments, an image sensor is configured to provide a time-series of frames. A first artificial neural network is operatively coupled to the image sensor and configured to detect a plurality of objects in the time-series of frames. A second artificial neural network is operatively coupled to the first artificial neural network and configured to classify objects detected by the first neural network and output a location and classification of said classified objects. The first and second artificial neural networks comprise one or more spike-based neurosynaptic cores.Type: ApplicationFiled: October 31, 2018Publication date: April 30, 2020Inventors: Alexander Andreopoulos, Arnon Amir, Tapan K. Nayak
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Publication number: 20200097801Abstract: Low spike count ring buffer mechanisms on neuromorphic hardware are provided. A ring buffer comprises a plurality of memory cells. The plurality of memory cells comprises one or more neurosynaptic core. A demultiplexer is operatively coupled to the ring buffer. The demultiplexer is adapted to receive input comprising a plurality of spikes, and write sequentially to each of the plurality of memory cells. A plurality of output connectors is operatively coupled to the ring buffer. Each of the plurality of output connectors is adapted to provide an output based on contents of a subset of the plurality of memory cells.Type: ApplicationFiled: September 24, 2018Publication date: March 26, 2020Inventor: Alexander Andreopoulos
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Publication number: 20200050883Abstract: Embodiments of the invention provide a computer-readable medium of visual saliency estimation comprising receiving an input video of image frames. Each image frame has one or more channels, and each channel has one or more pixels. The computer-readable medium further comprises, for each channel of each image frame, generating corresponding neural spiking data based on a pixel intensity of each pixel of the channel, generating a corresponding multi-scale data structure based on the corresponding neural spiking data, and extracting a corresponding map of features from the corresponding multi-scale data structure. The multi-scale data structure comprises one or more data layers, wherein each data layer represents a spike representation of pixel intensities of a channel at a corresponding scale. The computer-readable medium further comprises encoding each map of features extracted as neural spikes.Type: ApplicationFiled: October 15, 2019Publication date: February 13, 2020Inventors: Alexander Andreopoulos, Steven K. Esser, Dharmendra S. Modha
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Patent number: 10558892Abstract: Embodiments of the invention provide a method for scene understanding based on a sequence of image frames. The method comprises converting each pixel of each image frame to neural spikes, and extracting features from the sequence of image frames by processing neural spikes corresponding to pixels of the sequence of image frames. The method further comprises encoding the extracted features as neural spikes, and classifying the extracted features.Type: GrantFiled: September 28, 2018Date of Patent: February 11, 2020Assignee: International Business Machines CorporationInventors: Alexander Andreopoulos, Rathinakumar Appuswamy, Pallab Datta, Steven K. Esser, Dharmendra S. Modha
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Publication number: 20200034660Abstract: Embodiments of the invention provide a method for scene understanding based on a sequence of image frames. The method comprises converting each pixel of each image frame to neural spikes, and extracting features from the sequence of image frames by processing neural spikes corresponding to pixels of the sequence of image frames. The method further comprises encoding the extracted features as neural spikes, and classifying the extracted features.Type: ApplicationFiled: October 3, 2019Publication date: January 30, 2020Inventors: Alexander Andreopoulos, Rathinakumar Appuswamy, Pallab Datta, Steven K. Esser, Dharmendra S. Modha