Abstract: A processor includes a decode unit to decode a packed data alignment plus compute instruction. The instruction is to indicate a first set of one or more source packed data operands that is to include first data elements, a second set of one or more source packed data operands that is to include second data elements, at least one data element offset. An execution unit, in response to the instruction, is to store a result packed data operand that is to include result data elements that each have a value of an operation performed with a pair of a data element of the first set of source packed data operands and a data element of the second set of source packed data operands. The execution unit is to apply the at least one data element offset to at least a corresponding one of the first and second sets of source packed data operands. The at least one data element offset is to counteract any lack of correspondence between the data elements of each pair in the first and second sets of source packed data operands.

Abstract: A processor includes a decode unit to decode a packed data alignment plus compute instruction. The instruction is to indicate a first set of one or more source packed data operands that is to include first data elements, a second set of one or more source packed data operands that is to include second data elements, at least one data element offset. An execution unit, in response to the instruction, is to store a result packed data operand that is to include result data elements that each have a value of an operation performed with a pair of a data element of the first set of source packed data operands and a data element of the second set of source packed data operands. The execution unit is to apply the at least one data element offset to at least a corresponding one of the first and second sets of source packed data operands. The at least one data element offset is to counteract any lack of correspondence between the data elements of each pair in the first and second sets of source packed data operands.

Abstract: A processor includes a decode unit to decode a packed data alignment plus compute instruction. The instruction is to indicate a first set of one or more source packed data operands that is to include first data elements, a second set of one or more source packed data operands that is to include second data elements, at least one data element offset. An execution unit, in response to the instruction, is to store a result packed data operand that is to include result data elements that each have a value of an operation performed with a pair of a data element of the first set of source packed data operands and a data element of the second set of source packed data operands. The execution unit is to apply the at least one data element offset to at least a corresponding one of the first and second sets of source packed data operands. The at least one data element offset is to counteract any lack of correspondence between the data elements of each pair in the first and second sets of source packed data operands.

Abstract: A processor includes a decode unit to decode a packed data alignment plus compute instruction. The instruction is to indicate a first set of one or more source packed data operands that is to include first data elements, a second set of one or more source packed data operands that is to include second data elements, at least one data element offset. An execution unit, in response to the instruction, is to store a result packed data operand that is to include result data elements that each have a value of an operation performed with a pair of a data element of the first set of source packed data operands and a data element of the second set of source packed data operands. The execution unit is to apply the at least one data element offset to at least a corresponding one of the first and second sets of source packed data operands. The at least one data element offset is to counteract any lack of correspondence between the data elements of each pair in the first and second sets of source packed data operands.

Abstract: Method of generating respective instruction compaction schemes for subsets of instructions to be processed by a programmable processor, comprising the steps of a) receiving at least one input code sample representative for software to be executed on the programmable processor, the input code comprising a plurality of instructions defining a first set of instructions (S1), b) initializing a set of removed instructions as empty (S3), c) determining the most compact representation of the first set of instructions (S4) d) comparing the size of said most compact representation with a threshold value (S5), e) carrying out steps e1 to e3 if the size is larger than said threshold value, e1) determining which instruction of the first set of instructions has a highest coding cost (S6), e2) removing said instruction having the highest coding cost from the first set of instructions and (S7), e3) adding said instruction to the set of removed instructions (S8), f) repeating steps b-f, wherein the first set of instructions

Abstract: A programmed computer and method are described for generating a processor design. The method carried out by the programmed computer comprises providing an initial model for the processor, specifying a plurality of resources in terms of resource parameters and their mutual relations. Furthermore, statistics are provided indicative of the required use of the resources by a selected application. Thereafter, a reduced resource design is generated by the programmed computer by relaxing at least one resource parameter and/or limiting an amount of resources specified in the initial specification on the basis of the statistics.

Abstract: Method of generating respective instruction compaction schemes for subsets of instructions to be processed by a programmable processor, comprising the steps of a) receiving at least one input code sample representative for software to be executed on the programmable processor, the input code comprising a plurality of instructions defining a first set of instructions (S1), b) initializing a set of removed instructions as empty (S3), c) determining the most compact representation of the first set of instructions (S4) d) comparing the size of said most compact representation with a threshold value (S5), e) carrying out steps e1 to e3 if the size is larger than said threshold value, e1) determining which instruction of the first set of instructions has a highest coding cost (S6), e2) removing said instruction having the highest coding cost from the first set of instructions and (S7), e3) adding said instruction to the set of removed instructions (S8), f) repeating steps b-f, wherein the first set of instructions

Abstract: A processing apparatus is arranged to execute multiple-instruction words, a multiple-instruction word having a plurality of instructions. The processing apparatus comprises a plurality of issue slots (IS1, IS2) arranged for parallel execution of the plurality of instructions; a register file (RF1, RF2) accessible by the plurality of issue slots, and a communication network (CN) for coupling of the plurality of issue slots and the register file. The processing apparatus is further arranged to produce a first identifier (OV1) on the validity of first result data (RD1) produced by a first issue slot (IS1) and a second identifier (OV2) on the validity of second result data (RD2) produced by a second issue slot (IS2). The communication network comprises at least one selection circuit (SC1) arranged to dynamically control the transfer of either the first result data or the second result data to a register of the register file, in a single processor cycle, by using the first identifier and the second identifier.

Abstract: A processing system according to the invention comprises a plurality of processing elements (PE1, . . . , PE7). The processing elements comprise a controller and computation means. The plurality of processing elements is dynamically reconfigurable as mutually independently operating task units (TU1, TU2, TU3), which task units comprise one processing element (PE7) or a cluster of two or more processing elements (PE3, PE4, PE5, PE6). The processing elements within a cluster are arranged to execute instructions under a common thread of program control. In this way the processing system is capable of using the same sub-set of data-path elements to exploit instruction level parallelism or task level parallelism or a combination thereof, dependent on the application.

Abstract: A programmed computer and method are described for generating a processor design. The method carried out by the programmed computer comprises providing an initial model for the processor, specifying a plurality of resources in terms of resource parameters and their mutual relations. Furthermore, statistics are provided indicative of the required use of the resources by a selected application. Thereafter, a reduced resource design is generated by the programmed computer by relaxing at least one resource parameter and/or limiting an amount of resources specified in the initial specification on the basis of the statistics.

Abstract: A method is disclosed for partitioning a specification in a source code. In a first step, the specification is converted into a plurality of abstract syntax trees. In a second step, the plurality of abstract syntax trees is partitioned into at least a first set and a second set. The first set of abstract syntax trees is to be implemented by a first processor and the second set of abstract syntax trees is to be implemented by a second processor. The first and second set of abstracts syntax trees are translated to a specification in the original source code language, respectively, allowing the user to add manual changes to the specifications. Furthermore, specific compiler and design tools are used to convert the specifications into corresponding executable machine code and a specification of the co-processor.

Abstract: A processing apparatus is arranged to execute multiple-instruction words, a multiple-instruction word having a plurality of instructions. The processing apparatus comprises a plurality of issue slots (IS1, IS2) arranged for parallel execution of the plurality of instructions; a register file (RF1, RF2) accessible by the plurality of issue slots, and a communication network (CN) for coupling of the plurality of issue slots and the register file. The processing apparatus is further arranged to produce a first identifier (OV1) on the validity of first result data (RD1) produced by a first issue slot (IS1) and a second identifier (OV2) on the validity of second result data (RD2) produced by a second issue slot (IS2). The communication network comprises at least one selection circuit (SC1) arranged to dynamically control the transfer of either the first result data or the second result data to a register of the register file, in a single processor cycle, by using the first identifier and the second identifier.

Abstract: A threaded interpreter executes a program having a series of program instructions stored in a memory. For the execution of a program instruction the threaded interpreter includes a preparatory unit for executing a plurality of preparatory steps making th program instruction available in the threaded interpreter, and an execution unit with one or more machine instructions emulating the program instruction. The threaded interpreter is designed such that during the execution on an instruction-level parallel processor of the series of program instructions. Machine instructions implement a first one of the preparatory steps for execution in parallel with machine instructions implementing a second one of the preparatory steps for respective ones of the series of program instructions.

Abstract: A VLIW processor comprising: a plurality of functional units (1, 3); a distributed register file (4) comprising a plurality of segments (5, 7, 9), the distributed register file (4) being accessible by the functional units (1, 3); a communication unit (11) for communication with a memory; a communication network (13) for coupling the functional units (1, 3) and the distributed register file (4); characterized in that the VLIW processor further comprises a spilling device (15) for transferring data between the distributed register file (4) and the communication unit (11).

Abstract: The present invention provides a method and device for reconfiguring an embedded computing system during its lifetime, so that optimal trade-offs between performance and energy consumption can be achieved. An embedded computing system (10) according to the present invention comprises a plurality of domains, each domain (80, 82) comprising at least one processing element (12), each domain (80, 82) operating at a utility supply value, one domain (80, 82) having a first utility supply value. Each processing element (12) of the one domain is provided with a reconfiguration device for independently changing the utility supply value to a second utility supply value for the one domain.

Abstract: The present invention relates to a method and apparatus for decoding a sequence of at least two instructions of a data processing program into a sequence of code words used to control a data path, wherein an invariant code word portion which does not change in said sequence of code words is separately generated and used to configure a part of the data path to be fixed during the sequence of code words. Thereby, the necessary micro code memory size can be reduced and power consumption can be decreased.

Abstract: Target systems combining a number of different processors, for example a general-purpose processor (GP) and at least one co-processor (COP), or alternatively two or more co-processors (COPA, COPB, COPC), allow combining flexibility and speed for execution of a set of functions. The design of such target systems requires partitioning of a specification in a part to be implemented by the general-purpose processor and a part to be implemented by a co-processor, or into several parts to be implemented by different co-processors. The present invention describes a method for partitioning a specification in a source code. In a first step, the specification 301 is converted into a plurality of abstract syntax trees 101. In a second step, the plurality of abstract syntax trees 101 is partitioned into at least a first set 201 and a second set 203.

Abstract: A VLIW processor comprising: a plurality of functional units (1, 3); a distributed register file (4) comprising a plurality of segments (5, 7, 9), the distributed register file (4) being accessible by the functional units (1, 3); a communication unit (11) for communication with a memory; a communication network (13) for coupling the functional units (1, 3) and the distributed register file (4); characterized in that the VLIW processor further comprises a spilling device (15) for transferring data between the distributed register file (4) and the communication unit (11).

Abstract: A threaded interpreter (916) is suitable for executing a program comprising a series of program instructions stored in a memory (904). For the execution of a program instruction the threaded interpreter includes a preparatory unit (918) for executing a plurality of preparatory steps making the program instruction available in the threaded interpreter, and an execution unit (920) with one or more machine instructions emulating the program instruction. According to the invention, the threaded interpreter is designed such that during the execution on an instruction-level parallel processor of the series of program instructions machine instructions implementing a first one of the preparatory steps are executed in parallel with machine instructions implementing a second one of the preparatory steps for respective ones of the series of program instructions.

Abstract: A data processing device has a circuit for correcting an effect of executing memory access instructions out of order with respect to one another in a pipeline. A detector detects whether a same memory location is addressed by a first and second memory address used to access memory for a first and second memory access instruction that are processing at a predetermined relative distance in the pipeline respectively. A correction circuit modifies data handling in a pipeline stage processing the first memory access instruction when the detector signals the addressing of the same memory location and the first and/or second memory access instruction programs a command to compensate said effect of out of order execution of the first memory access instruction with respect to said second memory access instruction.