Patents by Inventor Alexander Badmaev
Alexander Badmaev has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955482Abstract: Integrated circuit structures having high phosphorous dopant concentrations are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. Each of the epitaxial structures of the first and second source or drain structures includes silicon and phosphorous, the phosphorous having an atomic concentration in a core region of the silicon greater than an atomic concentration in a peripheral region of the silicon.Type: GrantFiled: May 18, 2020Date of Patent: April 9, 2024Assignee: Intel CorporationInventors: Robert Ehlert, Timothy Jen, Alexander Badmaev, Shridhar Hegde, Sandrine Charue-Bakker
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Publication number: 20210358908Abstract: Integrated circuit structures having high phosphorous dopant concentrations are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. Each of the epitaxial structures of the first and second source or drain structures includes silicon and phosphorous, the phosphorous having an atomic concentration in a core region of the silicon greater than an atomic concentration in a peripheral region of the silicon.Type: ApplicationFiled: May 18, 2020Publication date: November 18, 2021Inventors: Robert EHLERT, Timothy JEN, Alexander BADMAEV, Shridhar HEGDE, Sandrine CHARUE-BAKKER
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Publication number: 20200194577Abstract: An HEMT semiconductor structure is disclosed. The semiconductor structure includes a substrate, a GaN layer above the substrate, a first TDD reducing structure above the substrate and a polarization layer above the GaN layer.Type: ApplicationFiled: December 13, 2018Publication date: June 18, 2020Inventors: Glenn GLASS, Sansaptak DASGUPTA, Han Wui THEN, Marko RADOSAVLJEVIC, Paul FISCHER, Anand MURTHY, Alexander BADMAEV, Michael S. BEUMER, Sandrine CHARUE-BAKKER
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Patent number: 8860137Abstract: RF transistors are fabricated at complete wafer scale using a nanotube deposition technique capable of forming high-density, uniform semiconducting nanotube thin films at complete wafer scale, and electrical characterization reveals that such devices exhibit gigahertz operation, linearity, and large transconductance and current drive.Type: GrantFiled: June 8, 2012Date of Patent: October 14, 2014Assignee: University of Southern CaliforniaInventors: Chongwu Zhou, Koungmin Ryu, Alexander Badmaev, Chuan Wang
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Patent number: 8778716Abstract: Techniques, apparatus and systems are described for wafer-scale processing of aligned nanotube devices and integrated circuits. In one aspect, a method can include growing aligned nanotubes on at least one of a wafer-scale quartz substrate or a wafer-scale sapphire substrate. The method can include transferring the grown aligned nanotubes onto a target substrate. Also, the method can include fabricating at least one device based on the transferred nanotubes.Type: GrantFiled: January 14, 2013Date of Patent: July 15, 2014Assignee: University of Southern CaliforniaInventors: Chongwu Zhou, Koungmin Ryu, Alexander Badmaev, Chuan Wang
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Patent number: 8692230Abstract: A high performance field-effect transistor includes a substrate, a nanomaterial thin film disposed on the substrate, a source electrode and a drain electrode formed on the nanomaterial thin film, and a channel area defined between the source electrode and the drain electrode. A unitary self-aligned gate electrode extends from the nanomaterial thin film in the channel area between the source electrode and the drain electrode, the gate electrode having an outer dielectric layer and including a foot region and a head region, the foot region in contact with a portion of the nanomaterial thin film in the channel area. A metal layer is disposed over the source electrode, the drain electrode, the head region of the gate electrode, and portions of the nanomaterial thin film proximate the source electrode and the drain electrode in the channel area.Type: GrantFiled: March 26, 2012Date of Patent: April 8, 2014Assignee: University of Southern CaliforniaInventors: Chongwu Zhou, Alexander Badmaev, Chuan Wang, Yuchi Che
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Patent number: 8618612Abstract: Techniques, apparatus and systems are described for wafer-scale processing of aligned nanotube devices and integrated circuits. In one aspect, a method can include growing aligned nanotubes on at least one of a wafer-scale quartz substrate or a wafer-scale sapphire substrate. The method can include transferring the grown aligned nanotubes onto a target substrate. Also, the method can include fabricating at least one device based on the transferred nanotubes.Type: GrantFiled: April 13, 2012Date of Patent: December 31, 2013Assignee: University of Southern CaliforniaInventors: Chongwu Zhou, Koungmin Ryu, Alexander Badmaev, Chuan Wang
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Publication number: 20130119348Abstract: RF transistors are fabricated at complete wafer scale using a nanotube deposition technique capable of forming high-density, uniform semiconducting nanotube thin films at complete wafer scale, and electrical characterization reveals that such devices exhibit gigahertz operation, linearity, and large transconductance and current drive.Type: ApplicationFiled: June 8, 2012Publication date: May 16, 2013Inventors: Chongwu Zhou, Alexander Badmaev, Chuan Wang
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Patent number: 8354291Abstract: Techniques, apparatus and systems are described for wafer-scale processing of aligned nanotube devices and integrated circuits. In one aspect, a method can include growing aligned nanotubes on at least one of a wafer-scale quartz substrate or a wafer-scale sapphire substrate. The method can include transferring the grown aligned nanotubes onto a target substrate. Also, the method can include fabricating at least one device based on the transferred nanotubes.Type: GrantFiled: November 24, 2009Date of Patent: January 15, 2013Assignee: University of Southern CaliforniaInventors: Chongwu Zhou, Koungmin Ryu, Alexander Badmaev, Chuan Wang
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Publication number: 20120261646Abstract: Techniques, apparatus and systems are described for wafer-scale processing of aligned nanotube devices and integrated circuits one. In one aspect, a method can include growing aligned nanotubes on at least one of a wafer-scale quartz substrate or a wafer-scale sapphire substrate. The method can include transferring the grown aligned nanotubes onto a target substrate. Also, the method can include fabricating at least one device based on the transferred nanotubes.Type: ApplicationFiled: April 13, 2012Publication date: October 18, 2012Inventors: Chongwu Zhou, Koungmin Ryu, Alexander Badmaev, Chuan Wang
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Publication number: 20120248416Abstract: A high performance field-effect transistor includes a substrate, a nanomaterial thin film disposed on the substrate, a source electrode and a drain electrode formed on the nanomaterial thin film, and a channel area defined between the source electrode and the drain electrode. A unitary self-aligned gate electrode extends from the nanomaterial thin film in the channel area between the source electrode and the drain electrode, the gate electrode having an outer dielectric layer and including a foot region and a head region, the foot region in contact with a portion of the nanomaterial thin film in the channel area. A metal layer is disposed over the source electrode, the drain electrode, the head region of the gate electrode, and portions of the nanomaterial thin film proximate the source electrode and the drain electrode in the channel area.Type: ApplicationFiled: March 26, 2012Publication date: October 4, 2012Applicant: UNIVERSITY OF SOUTHERN CALIFORNIAInventors: Chongwu Zhou, Alexander Badmaev, Chuan Wang, Yuchi Che
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Publication number: 20110101302Abstract: Methods, materials, systems and apparatus are described for depositing a separated nanotube networks, and fabricating, separated nanotube thin-film transistors and N-type separated nanotube thin-film transistors. In one aspect, a method of depositing a wafer-scale separated nanotube networks includes providing a substrate with a dielectric layer. The method includes cleaning a surface of the wafer substrate to cause the surface to become hydrophilic. The cleaned surface of the wafer substrate is functionalized by applying a solution that includes linker molecules terminated with amine groups. High density, uniform separated nanotubes are assembled over the functionalized surface by applying to the functionalized surface a separated nanotube solution that includes semiconducting nanotubes.Type: ApplicationFiled: November 5, 2010Publication date: May 5, 2011Applicant: UNIVERSITY OF SOUTHERN CALIFORNIAInventors: Chongwu Zhou, Chuan Wang, Jialu Zhang, Koungmin Ryu, Alexander Badmaev, Lewis Gomez De Arco
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Publication number: 20100133511Abstract: Techniques, apparatus and systems are described for wafer-scale processing of aligned nanotube devices and integrated circuits. In one aspect, a method can include growing aligned nanotubes on at least one of a wafer-scale quartz substrate or a wafer-scale sapphire substrate. The method can include transferring the grown aligned nanotubes onto a target substrate. Also, the method can include fabricating at least one device based on the transferred nanotubes.Type: ApplicationFiled: November 24, 2009Publication date: June 3, 2010Inventors: Chongwu Zhou, Koungmin Ryu, Alexander Badmaev, Chuan Wang