Abstract: The invention provides a method for storing data in a memory device having memory cells arranged in memory cell rows and memory cell columns, in which system defects brought about by defective memory cells are eliminated, in which case redundant memory cells are provided in the memory device; a predeterminable access mode for accessing the redundant memory cells is provided; and defective memory cells of the memory device are replaced by the redundant memory cells in a manner dependent on the predetermined access mode during operation of the memory device.

Abstract: A temperature sensor is integrated together with an integrated circuit on a chip, the sensor delivering a temperature-dependent measuring signal or at least emitting a signal when the chip temperature falls below a specific prescribed value. For such an eventuality, the chip includes a special circuit device thereon, by which a current flow is generated through a provided structure of electrical conductors that keeps the temperature of the integrated circuit above a prescribed minimum temperature.

Abstract: A dynamic semiconductor memory and a method for operating such a memory includes memory banks with memory cells disposed in rows, and registers associated with the memory banks for storing an address of an open, activated word line. In the event of an external refresh command, a control device causes, after the refresh operation, the state of the memory banks to be reestablished, in particular, the word line whose address was stored in the register to be reactivated. Such a purely on-chip measure increases the operating speed of the memory.

Abstract: The present invention relates to an interconnect structure for an integrated circuit (1) having a first interconnect (B1; B1′; B1″), which is composed of a plurality of interconnect sections (A11-A16; A11′-A16′; A11″-A14″) lying in a first and a second interconnect plane (M0, M1); and a second interconnect (B2; B2′; B2″), which runs adjacent to the first interconnect (B1; B1′; B1″) and which is composed of a plurality of interconnect sections (A21-A25; A21′-A25′; A21″-A23″) lying in the first and second interconnect planes (M0, M1); the first and second interconnects (B1; B1′; B1″; B2; B2′; B2″) being offset with respect to one another in the longitudinal direction in such a way that the interconnect sections (A12, A14, A16; A12′, A14′, A16′; A12″, A14″) of the first interconnect (B1; B1′; B1″) which lie in the first interconnect plane (M0) run at least in secti

Abstract: The data processing system has configurable components, which each have a configuration register for storing configuration data. A serial bus couples the configuration registers to a non-volatile memory so that a serial transmission of data from the non-volatile memory to the configuration registers is made possible, for example when the system is booted up. The system already functions even if complex bus systems, such as extensively parallel high-speed buses, for example, are not yet available in a configuration process of the system. The system can be used in all data processing systems, in particular in mobile applications.

Abstract: The invention relates to dynamic memories having at least one memory matrix (1) having a plurality of memory cells arranged in rows and columns, the memory cells in a row being connected by in each case one of a plurality of word lines and the memory cells in a column being connected by in each case one of a plurality of bit lines, at least one sense amplifier (13) for reading data from the memory cells via the plurality of bit lines, at least one row address decoder and at least one column address decoder (12) for generating a memory-internal address in a manner dependent on a memory-external address signal, a sequence control device (7) for cyclically generating refresh addresses for carrying out a refresh operation of the memory cells.

Abstract: A semiconductor configuration is described and has a temperature sensor, which measures a temperature of a semiconductor module. The measured temperature is provided to a control unit, so that the control unit can adapt a refresh cycle in the semiconductor module to the retention time corresponding to the measured temperature.

Abstract: To be able to test a plurality of identical semiconductor circuit devices in a particularly rapid yet reliable manner, a test method includes carrying out the tests in parallel and substantially simultaneously on the plurality of semiconductor circuit devices and driver lines—used in the process—of a test device to the semiconductor circuit devices simultaneously and jointly for all the semiconductor circuit devices. In such a case, test results are read from a plurality of input/output channels in compressed form. Furthermore, as an alternative or in addition thereto, the semiconductor circuit devices to be tested are disposed and connected up in at least one stack.

Abstract: A method for integrating imperfect semiconductor memory devices having functional and defective memory cells into a data processing apparatus. The defective memory cells are assigned defect addresses or defect address ranges. Before a memory access of the data processing apparatus is carried out, the address of the memory access is compared with the defect addresses or defect address ranges and is recoded in the event of correspondence.

Abstract: A method for replacing defective memory cells of a random access memory device of a data processing apparatus, in which, during the operation of the data processing apparatus, a defective memory cell is replaced by a replacement memory cell in the random access memory device by using a control instruction.

Abstract: A description is given of a method and a device for outputting data via a buffer memory. In which the data, which are intended to be output first from the buffer memory are selected. The selected data are written either to a predetermined area of the buffer memory and/or to the buffer memory temporally before the rest of the data and output.

Abstract: An interface unit and a printed circuit board configuration includes at least two interface units for linking conventional commercially available packages of integrated circuits on a printed circuit board in a more flexible and compact way, which allows compact high-performance electronic circuits to be produced on a small surface area and with low development expenditure.

Abstract: The data processing device has a processor with a cache memory, a system memory that can be connected to the processor, and a translation unit that can convert an external instruction or a group of external instructions into internal instructions by a translation process. The translation unit is formed by a computing unit assigned to the system memory, for carrying out the translation processes using the system memory.

Abstract: An integrated memory has a memory cell array, which is subdivided into a plurality of separate segments. A first and a second local word line in different segments together form a common global word line. The global word line is decoded via a row decoder. The first and second local word lines are connected to a column decoder in such a way that they can be decoded individually and segment by segment in a manner dependent on a column address. The memory thus allows fast and current-saving activation of a word line.

Abstract: A semiconductor memory is described which has a clock input, a signal input, a data output, a measuring device, a control circuit, and a latency. The latency elapses between the activation of the signal input and the availability of the data to be read at the data output. A clock signal is fed to the clock input. On the basis of the clock signal, the measuring device determines a value for the latency and the control circuit configures the semiconductor memory with the determined value for the operation of the semiconductor memory.

Abstract: The semiconductor configuration has a packing material that is permeable to radiation energy in a given wavelength band. One or more fuses that adjoin the packing material absorb the energy in the given wavelength band. The fuses are formed of AIIIBV semiconductor material, of titanium silicide, germanium, PbS, InSb, or of SiGe.

Abstract: A dynamic semiconductor memory and a method for operating such a memory includes memory banks with memory cells disposed in rows, and registers associated with the memory banks for storing an address of an open, activated word line. In the event of an external refresh command, a control device causes, after the refresh operation, the state of the memory banks to be reestablished, in particular, the word line whose address was stored in the register to be reactivated. Such a purely on-chip measure increases the operating speed of the memory.

Abstract: A description is given of a method and a device for outputting data via a buffer memory. In which the data, which are intended to be output first from the buffer memory are selected. The selected data are written either to a predetermined area of the buffer memory and/or to the buffer memory temporally before the rest of the data and output.

Abstract: A semiconductor configuration is described and has a temperature sensor, which measures a temperature of a semiconductor module. The measured temperature is provided to a control unit, so that the control unit can adapt a refresh cycle in the semiconductor module to the retention time corresponding to the measured temperature.

Abstract: Data in a memory unit are processed with one of a variety of access strategies. Parallel to the execution of a task according to a first access strategy, the time is calculated that would be required for the processing of the task according to a second access strategy. If the second access strategy is faster than the first access strategy, in the future the second access strategy is used for the execution of that task. In this way, a faster data access, adapted to various tasks, is achieved.