Patents by Inventor Alexander Borisovich Kholodenko

Alexander Borisovich Kholodenko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9542748
    Abstract: Systems and methods for image processing may perform one or more operations including, but not limited to: receiving raw image data from at least one imaging device; computing at least one image depth distance from the raw image data; computing one or more image validity flags from the raw image data; generating at least one data validity mask from the one or more image validity flags; determining a background imagery estimation from at least one image depth distance; generating at least one foreground mask from the background imagery estimation and the at least one image depth distance; generating at least one region-of-interest mask from the data validity mask and the foreground mask; and generating filtered raw image data from the raw image data and at least one region of interest mask.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: January 10, 2017
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Ivan Leonidovich Mazurenko, Pavel Aleksandrovich Aliseitchik, Alexander Borisovich Kholodenko, Denis Vasilyevich Parfenov, Denis Vladimirovich Parkhomenko
  • Patent number: 9336431
    Abstract: A method and system for key frame based region of interest (ROI) tracking is disclosed. The method includes storing a key ROI set in a key ROI buffer, the key ROI set including at least one key ROI; designating one of the key ROI in the key ROI set as an active key ROI; receiving a point cloud representing a particular ROI to be processed for tracking; establishing a correspondence between that particular ROI and the active key ROI; determining whether to switch the active key designation to another key ROI in the key ROI set and switching the active key designation accordingly; and determining whether to modify the key ROI set and modifying the key ROI set accordingly.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: May 10, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Ivan Leonidovich Mazurenko, Alexander Alexandrovich Petyushko, Denis Vladimirovich Parkhomenko, Alexander Borisovich Kholodenko, Dmitry Nicolaevich Babin
  • Publication number: 20150310622
    Abstract: In one embodiment, an image processor is configured to obtain phase images, and to group the phase images into pseudoframes with each of at least a subset of the pseudoframes comprising multiple ones of the phase images and having as a first phase image thereof one of the phase images that is not a first phase image of an associated depth frame. A velocity field is estimated by comparing corresponding phase images in respective ones of the pseudoframes. Phase images of one or more pseudoframes are modified based at least in part on the estimated velocity field, and one or more depth images are generated based at least in part on the modified phase images. By way of example, different groupings of the phase images into pseudoframes may be used for each obtained phase image, allowing depth images to be generated at much higher rates than would otherwise be possible.
    Type: Application
    Filed: April 1, 2015
    Publication date: October 29, 2015
    Inventors: Alexander Borisovich Kholodenko, Barrett J. Brickner, Denis Vladimirovich Zaytsev, Denis Vasilyevich Parfenov, Alexander Alexandrovich Petyushko
  • Publication number: 20150302593
    Abstract: Systems and methods for image processing may perform one or more operations including, but not limited to: receiving raw image data from at least one imaging device; computing at least one image depth distance from the raw image data; computing one or more image validity flags from the raw image data; generating at least one data validity mask from the one or more image validity flags; determining a background imagery estimation from at least one image depth distance; generating at least one foreground mask from the background imagery estimation and the at least one image depth distance; generating at least one region-of-interest mask from the data validity mask and the foreground mask; and generating filtered raw image data from the raw image data and at least one region of interest mask.
    Type: Application
    Filed: April 8, 2013
    Publication date: October 22, 2015
    Applicant: LSI Corporation
    Inventors: Ivan Leonidovich Mazurenko, Pavel Aleksandrovich Aliseitchik, Alexander Borisovich Kholodenko, Denis Vasilyevich Parfenov, Denis Vladimirovich Parkhomenko
  • Publication number: 20150286859
    Abstract: An image processing system comprises an image processor having image processing circuitry and an associated memory. The image processor is configured to implement an object tracking module. The object tracking module is configured to obtain one or more images, to extract contours of at least two objects in at least one of the images, to select respective subsets of points of the contours for the at least two objects based at least in part on curvatures of the respective contours, to calculate features of the subsets of points of the contours for the at least two objects, to detect intersection of the at least two objects in a given image, and to track the at least two objects in the given image based at least in part on the calculated features responsive to detecting intersection of the at least two objects in the given image.
    Type: Application
    Filed: March 31, 2015
    Publication date: October 8, 2015
    Inventors: Denis Vladimirovich Zaytsev, Denis Vasilyevich Parfenov, Pavel Aleksandrovich Aliseitchik, Denis Vladimirovich Parkhomenko, Alexander Borisovich Kholodenko
  • Publication number: 20150278589
    Abstract: An image processing system comprises an image processor having image processing circuitry and an associated memory. The image processor is configured to implement a gesture recognition system utilizing the image processing circuitry and the memory. The gesture recognition system implemented by the image processor comprises a static pose recognition module. The static pose recognition module is configured to identify a hand region of interest in at least one image, to determine a contour of the hand region of interest, to triangulate the determined contour, to flatten the triangulated contour, to compute one or more features of the flattened contour, and to recognize a static pose of the hand region of interest based at least in part on the one or more computed features.
    Type: Application
    Filed: March 25, 2015
    Publication date: October 1, 2015
    Inventors: Ivan Leonidovich Mazurenko, Alexander Borisovich Kholodenko, Dmitry Nicolaevich Babin, Aleksey Alexandrovich Letunovskiy, Alexander Alexandrovich Petyushko
  • Publication number: 20150278582
    Abstract: An image processing system comprises an image processor having image processing circuitry and an associated memory. The image processor is configured to implement a face recognition system utilizing the image processing circuitry and the memory, the face recognition system comprising a face recognition module. The face recognition module is configured to identify a region of interest in each of two or more images, to extract a three-dimensional representation of a head from each of the identified regions of interest, to transform the three-dimensional representations of the head into respective two-dimensional grids, to apply temporal smoothing to the two-dimensional grids to obtain a smoothed two-dimensional grid, and to recognize a face based on a comparison of the smoothed two-dimensional grid and one or more face patterns.
    Type: Application
    Filed: March 25, 2015
    Publication date: October 1, 2015
    Inventors: Alexander Alexandrovich Petyushko, Denis Vladimirovich Zaytsev, Pavel Aleksandrovich Aliseitchik, Denis Vladimirovich Parkhomenko, Alexander Borisovich Kholodenko
  • Patent number: 9037944
    Abstract: A method for estimating error probability of LDPC codes includes ordering LDPC codes according to features in each code with known error characteristics. The method includes identifying features in each LDPC code having known error characteristics; adding each code to one or more categories based on the existence of such features; and ranking the LDPC codes according to the level of error risk.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: May 19, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Alexander Alexandrovich Petyushko, Anatoli Aleksandrovich Bolotov, Yang Han, Ivan Leonidovich Mazurenko, Alexander Borisovich Kholodenko, Denis Vladimirovich Zaytsev, Denis Vasilievich Parfenov
  • Publication number: 20140226854
    Abstract: A method and system for key frame based region of interest (ROI) tracking is disclosed. The method includes storing a key ROI set in a key ROI buffer, the key ROI set including at least one key ROI; designating one of the key ROI in the key ROI set as an active key ROI; receiving a point cloud representing a particular ROI to be processed for tracking; establishing a correspondence between that particular ROI and the active key ROI; determining whether to switch the active key designation to another key ROI in the key ROI set and switching the active key designation accordingly; and determining whether to modify the key ROI set and modifying the key ROI set accordingly.
    Type: Application
    Filed: August 22, 2013
    Publication date: August 14, 2014
    Applicant: LSI Corporation
    Inventors: Ivan Leonidovich Mazurenko, Alexander Alexandrovich Petyushko, Denis Vladimirovich Parkhomenko, Alexander Borisovich Kholodenko, Dmitry Nicolaevich Babin
  • Publication number: 20140226895
    Abstract: A method and system for registration of three-dimensional (3D) image frames is disclosed. The method includes receiving two point clouds representing two 3D image frames obtained at two time instances; locating the origins for the two point clouds; constructing two 2D grids for representing the two point clouds, wherein each 2D grid is constructed based on spherical representation of its corresponding point cloud and origin; identifying two sets of feature points based on the two 2D grids constructed; establishing a correspondence between the first set of feature points and the second set of feature points based on a neighborhood radius threshold; and determining an orthogonal transformation between the first 3D image frame and the second 3D image frame based on the correspondence between the first set of feature points and the second set of feature points.
    Type: Application
    Filed: August 21, 2013
    Publication date: August 14, 2014
    Applicant: LSI Corporation
    Inventors: Dmitry Nicolaevich Babin, Alexander Alexandrovich Petyushko, Ivan Leonidovich Mazurenko, Alexander Borisovich Kholodenko, Denis Vladimirovich Parkhomenko
  • Publication number: 20140193092
    Abstract: Superresolution image processing that can be applied when two image frames of the same scene are available so that image information from one frame can be used to enhance the image from the other frame. The superresolution image processing uses a sparse matrix generated based on a Markov random field defined over these two image frames. The sparse matrix is inverted and applied to the image data from the image frame that is being enhanced to generate a corresponding enhanced image.
    Type: Application
    Filed: July 25, 2013
    Publication date: July 10, 2014
    Applicant: LSI CORPORATION
    Inventors: Alexander Alexandrovich Petyushko, Dmitry Nikolaevich Babin, Ivan Leonidovich Mazurenko, Alexander Borisovich Kholodenko
  • Patent number: 8713495
    Abstract: A computer-aided design method for developing, simulating, and testing a read-channel architecture to be implemented in a VLSI circuit. The method uses a coset operating mode and nonzero-syndrome-based decoding to accelerate the simulation of the read-channel's error-rate characteristics corresponding to different parity-check matrices employed in the read-channel's turbo-decoder, such as a low-density parity-check decoder. The acceleration is achieved through recycling some previously generated log-likelihood-ratio values, which enables the method to sometimes bypass certain time-consuming processing steps therein.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: April 29, 2014
    Assignee: LSI Corporation
    Inventors: Pavel Aleksandrovich Aliseychik, Aleksey Alexandrovich Letunovskiy, Alexander Alexandrovich Petyushko, Denis Vladimirovich Parkhomenko, Alexander Borisovich Kholodenko
  • Publication number: 20140053038
    Abstract: A method for estimating error probability of LDPC codes includes ordering LDPC codes according to features in each code with known error characteristics. The method includes identifying features in each LDPC code having known error characteristics; adding each code to one or more categories based on the existence of such features; and ranking the LDPC codes according to the level of error risk.
    Type: Application
    Filed: November 8, 2012
    Publication date: February 20, 2014
    Applicant: LSI CORPORATION
    Inventors: Alexander Alexandrovich Petyushko, Anatoli Aleksandrovich Bolotov, Yang Han, Ivan Leonidovich Mazurenko, Alexander Borisovich Kholodenko, Denis Vladimirovich Zaytsev, Denis Vasilievich Parfenov
  • Publication number: 20140053121
    Abstract: A computer-aided design method for developing, simulating, and testing a read-channel architecture to be implemented in a VLSI circuit. The method uses a coset operating mode and nonzero-syndrome-based decoding to accelerate the simulation of the read-channel's error-rate characteristics corresponding to different parity-check matrices employed in the read-channel's turbo-decoder, such as a low-density parity-check decoder. The acceleration is achieved through recycling some previously generated log-likelihood-ratio values, which enables the method to sometimes bypass certain time-consuming processing steps therein.
    Type: Application
    Filed: February 28, 2013
    Publication date: February 20, 2014
    Applicant: LSI CORPORATION
    Inventors: Pavel Aleksandrovich Aliseychik, Aleksey Alexandrovich Letunovskiy, Alexander Alexandrovich Petyushko, Denis Vladimirovich Parkhomenko, Alexander Borisovich Kholodenko