Abstract: A timing estimation mechanism operative to generate an oversampling clock signal for a large range of reference clock frequencies without requiring use of a PLL. The oversampling timing mechanism generates appropriate timing instances, typically for the purpose of sampling a received data signal in a digital communications system, without requiring a specific external clock source but rather by utilizing a clock source having any arbitrary frequency. The mechanism of the present invention is especially suited for use in applications where a specific external clock source (e.g., integer multiple of the data rate) is not available and wherein the implications of the use of a PLL cannot be tolerated. The oversampling clock estimation mechanism generates a clock signal which may be unevenly distributed over the symbol period, but whereby on average, the correct number of samples is produced over a specific time duration.

Abstract: A novel and useful apparatus for and method of clock recovery from a serial data stream. The clock recovery mechanism of the present invention provides accurate and fast timing recovery while operative to filter out the effects of noise. The clock recovery mechanism clocks the received serial data into a shift register of N bits, where N is an even number equal to the oversampling factor of the data signal. A timing correction, generated during learning cycles, is applied during the subsequent correction cycle. The timing is adjusted during correction cycles by preloading the reference counter, from which the sampling clock is produced, such that its cycle is either shortened or extended by M clocks, where M corresponds to the required timing correction.

Abstract: A glitch free self-correcting clock switching mechanism operative to switch between two clocks in a glitch free manner while compensating for the ambiguity inherent in the switching operation. During the switching from fast to slow clock domains the mechanism measures the uncertainty or ambiguity of the first slow clock cycle duration during the switching operation and stores this value. At some time later, during the slow to fast clock switching the clock switch mechanism compensates for the metastability of the first slow clock cycle during fast to slow switching using the ambiguity value previously measured. In this manner the fast and slow clocks are switched between each other in a glitch-free and self compensating manner.

Abstract: A novel and useful mechanism for measuring the time duration between asynchronous events. The mechanism utilizes two metastability resolvers, one for detecting the rising edge of the input signal and one for detecting its falling edge. The input signal is typically assumed to have some known nominal clock rate, but its exact frequency and phase (timing of transitions) are not known. Each of the two metastability resolvers comprises two branches of cascaded flip flops, each clocked off the rising edge and falling edge of a fast clock. Each metastability resolver functions to output an edge event signal and a clock phase signal indicating which edge of the fast clock the rising (or falling) edge of the data signal was closer to. The edge event signals are used to start and stop a counter clocked off the fast clock. The clock phase is used to correct (i.e. compensate) the counter value depending on which half cycle of the fast clock the rising and falling edge of the data signal arrived in.

Abstract: A novel and useful apparatus for and method of clock recovery from a serial data stream. The clock recovery mechanism of the present invention provides accurate and fast timing recovery while operative to filter out the effects of noise. The clock recovery mechanism clocks the received serial data into a shift register of N bits, where N is an even number equal to the oversampling factor of the data signal. A timing correction, generated during learning cycles, is applied during the subsequent correction cycle. The timing is adjusted during correction cycles by preloading the reference counter, from which the sampling clock is produced, such that its cycle is either shortened or extended by M clocks, where M corresponds to the required timing correction.